Webinars 

As the complexity of systems-on-chip increases, so does the need to leverage standards-based methodologies to implement test in a hierarchical manner, across multiple cores.
Dr. Saman Adham, Senior Manager, TSMC; Robert Ruiz, Product Marketing Manager, Synopsys; Adam Cron, Principal Engineer, Synopsys
May 23, 2013

Increased design size and complexity can lead to exponential growth in turn-around-time (TAT). This webinar describes the methodology Fujitsu developed using DC Explorer and Design Compiler Graphical to achieve faster design convergence and reduced TAT on large, 40 million+ instance designs. You will hear how DC Explorer speeds up the development of high-quality RTL and constraints and generates an early netlist for guiding and optimizing floorplanning. This early floorplan exploration helps identify layout issues and provides more accurate area estimation up-front in the design flow to help create optimal design partitions, with a better starting point for implementation. Learn how Fujitsu then uses Design Compiler Graphical to achieve higher performance and tighter correlation with place and route for faster design convergence.
Koji Inoue, Corporate Application Engineer, Synopsys
Dec 06, 2012

Hear how Xilinx is using SSI technology to deliver higher levels of integration and flexibility in FPGA products, and learn how Synopsys' silicon-proven tools are enabling 3D-IC integration.
Steve Smith, Senior Director, 3D-IC Strategy and Marketing, Synopsys; Shankar Lakka, Director of IC Design, Full-Chip FPGA Integration Group, Xilinx
Jul 18, 2012

Jack Randall, principal member of the technical staff at AMD, describes his design methodology for implementing a low power, multi-million instance processor core with the latest Design Compiler technologies.
Jack Randall, Principal Member of Technical Staff, AMD; Sandra Ma, Group Director of Corporate Applications, Synopsys
Jun 19, 2012

Learn how to use Synopsys' synthesis-based test solution to reduce test cost and improve test quality for designs with few available test pins, and for designs with multiple power domains.
Robert Ruiz, Senior Product Marketing Manager, Synopsys; Carl Holzwarth Corporate Applications Engineering Director, Synopsys; and Brad MacMonagle Senior Staff Applications Consultant, Synopsys
May 23, 2012

Learn how Formality utilizes powerful links with Design Compiler that enable you to achieve maximum Quality of Results (QoR) while maintaining verifiability.
Joe Bosia, Corporate Applications Engineer, Synopsys
May 03, 2012

Learn how DC Explorer enables early RTL exploration leading to a better starting point for RTL synthesis and accelerates design implementation.
Matt Baker, Staff Engineer, Qualcomm; Sandra Ma, Sr. Director, Corporate Application Engineer, Synopsys; Liz Chambers, Product Marketing Manager, Synopsys
Nov 01, 2011

Hear about the new ECO Verification capabilities in Formality and other key new features, including its low power library checker, ease of use improvements and runtime enhancements.
Mark Patton, Product Marketing Director, Synopsys; David Low, Corporate Applications Engineer, Synopsys
Oct 27, 2011

In this webinar you will learn how various ways of describing power intent with IEEE 1801 (UPF) can help you achieve more efficient low power designs. You will also have the opportunity to engage in an interactive Q&A session following the technical presentation.
Somil Ingle, Corporate Applications Engineer, Synopsys; Mary Ann White, Product Marketing Director, Synopsys
Oct 12, 2011

Learn how the use of SystemVerilog constructs can result in concise, portable RTL that is easier to maintain and consistent with verification requirements.
Liz Chambers, Product Marketing Manager for Design Compiler, Synopsys; James Argraves, Corporate Applications Engineering Manager for HDL Compiler, Synopsys
Apr 27, 2011

See how new Design Compiler 2010 technologies double the productivity of synthesis and P&R by enabling RTL designers to perform floorplan exploration while still in synthesis.
Sandra Ma, Sr. Director, Corporate Application Engineer, Alak Ghosh, Staff Corporate Application Engineer Webinar
Jul 22, 2010

This webinar will address what to do when faced with an inconclusive for non-equivalent design in Formality. Common types of failures will be discussed as well as suggestions for resolving them. New features in Formality 2010.03 will be presented which help the designer quickly identify the sources of the issue and makes recommendations on how to resolve them. Recent Formality low power enhancements will also be discussed.
Mitch Milner, R&D Group Director of Formal Verification
Jun 24, 2010

Learn about a new capability in Design Compiler that allows RTL designers to perform floorplan exploration from within the synthesis environment to efficiently achieve an optimal floorplan. Hear about Design Compiler’s new scalable infrastructure tuned for multicore processors yielding 2X faster synthesis runtimes on quad-core compute servers.
Janet Olson, Sr. Director, R&D, Synopsys; Sandra Ma, Sr. Director, Corporate Applications Engineer, Synopsys
Apr 20, 2010

Join us for an in-depth technical webinar focused on how to achieve successful verification on high-performance designs compiled with DC Ultra.
Mitchell Mliner, Synopsys
Apr 21, 2009

Join this webinar to hear directly from senior product team members on how you can achieve superior results faster utilizing sophisticated optimizations of DC Ultra.
Sandra Ma, Synopsys; Janet Olson, Synopsys
Apr 21, 2009