Physical Verification in the Synopsys Galaxy™ Design Platform provides technology-leading, production-proven solutions for design rule checking (DRC), layout verification (LVS), and practical DFM applications such as lithography compliance checking (LCC). The Physical Verification solution offers production-proven and foundry-certified signoff through 32 nanometers coupled with productivity links to leading design tools such as IC Compiler physical design, StarRC parasitic extraction and Custom Designer mixed-signal design. The latest signoff DRC/LVS offering, IC Validator, is architected for in-design Physical Verification within IC Compiler.