|IC Validator Programmable EERC Netlist Domain Checking Technology|
Traditional visual inspection or manual checking for electrical rule compliance is both time consuming and error prone. A new, comprehensive reliability solution is needed to reduce time to market, improve reliability and ensure longer device operation. This paper introduces IC Validator programmable Extended Electrical Rule Checking (EERC) and categorizes electrical rule checking (ERC) into three broad categories: netlist domain, mixed mode and current density / point-to-point resistance. The focus of this first of three white papers is on the netlist domain class of checks.
Harvey Toyama, Product Marketing Manager, Synopsys, Inc.
|IC Validator Programmable EERC Mixed Mode Checking Technology|
Traditional visual inspection or manual checking for electrical rule compliance is both time consuming and error prone. A new, comprehensive reliability solution is needed to reduce time to market, improve reliability and ensure longer device operation. This paper is a companion to the introductory IC Validator programmable Extended Electrical Rule Check (EERC) white paper on netlist domain checking. IC Validator programmable EERC categorizes electrical rule checking (ERC) into three broad categories: netlist domain, mixed mode and current density/point-to-point resistance. This paper focuses on the mixed mode class of checks.
Harvey Toyama, Product Marketing Manager, Synopsys, Inc.
|IC Validator and In-Design Metal Fill in IC Compiler II|
Metal fill has evolved from an afterthought performed by the foundries to a mission critical design requirement that customers now carefully design themselves in order to achieve high yield and maximum design timing performance. IC Validator and In-Design metal fill in IC Compiler II is architected to be the ideal comprehensive unified fill solution at 20-nm and below.
|Accelerating 20nm Double Patterning Verification|
This whitepaper presents the key concepts of DPT compliant design and demonstrates how new signoff technology in IC Validator makes it possible to ensure 20nm manufacturing compliance. Recognizing that the designer productivity necessary cannot be achieved alone by point-tool enhancements and post-processing techniques, the paper outlines advances in In-Design physical verification within IC Compiler.
Paul Friedberg, CAE, Synopsys; Stelios Diamantidis, Product Marketing, Synopsys
|Physical Verification of FinFETs and Fully Depleted SOI|
It has come to be broadly accepted in the semiconductor industry that short-channel effects severely limit bulk planar transistor performance, and alternative device structures will necessarily have to be adopted if we are to shrink process geometries below 20nm. This paper explores the two major contenders for the new transistor architecture: finFETs and fully depleted silicon-on-insulator.
Ron Duncan, Applications Engineering Manager, Synopsys; Marc Swinnen, Product Marketing Manager, Synopsys
|FinFET Technology – Understanding and Productizing a New Transistor From TSMC and Synopsys|
This white paper discusses the major challenges with FinFETs and how TSMC has been collaborating with
Synopsys, one of their ecosystem partners, to deliver a complete solution. Key elements of this solution include
comprehensive FinFET profiling without impact to design tool runtime and proven, verified IP availability. The
TSMC 16-nm FinFET solution will ensure mutual customers swiftly move to building the next generation SoCs.
Jason S.T. Chen, TSMC; Andy Biddle, Synopsys
|IC Validator: Automatic DRC Repair|
This paper presents how in-design physical verification with IC
Validator enables Automatic DRC Repair (ADR), a novel capability that makes it possible for designers to
automatically detect, repair and revalidate signoff DRC violations with negligible physical or timing impact, all within IC Compiler.
Paul Friedberg, Staff CAE
|IC Validator: GDS Merge|
With today’s increasingly complicated design flows, creating a snapshot of a design’s full mask set to run physical verification at intermediate points during the design cycle, or in-design, presents many challenges. This paper presents an optimal approach to creating a working snapshot of a design’s complete mask data set for the purposes of in-design physical verification with IC Validator, Synopsys’ award-winning physical verification platform for advanced nodes.
Rich Santilli, Staff CAE
|IC Validator: Physical Verification for Analog Designs|
Physical verification challenges of analog designs are different than the challenges of large digital designs. In addition to complex runset requirements, a tight interface to a parasitic extraction tool and an easy-to-use GUI are needed to use a runset effectively in an analog design environment. IC Validator, the latest generation physical verification tool, can be used to solve these issues. This paper addresses many of the physical verification requirements of analog designers and how they are met with IC Validator.
Al Blais, Global Technology Services
|Following the Rules is Not Quite Sufficient|
Smaller technologies, shorter time to market windows and more complex designs are driving the need for an
additional set of analysis techniques which will help designers understand how susceptible their designs are
to manufacturing process variations Technology nodes larger than 90 nm were able to achieve a certain level
of manufacturability by complying with a set of foundry design rules.
Kuo H. Wu, PhD and Marilyn Adan
|Achieving Optimal Performance Scalability for Physical Verification|
Physical verification runtimes and memory usage have exploded with the increasing number of design
rules, their subsequent complexity and the size of chips to be verified.
Rahul Kapoor, Marilyn Adan, and Louis Schaffer
|Accelerating Physical Verification with an In-Design Flow|
There is a growing need for a concurrent physical design and physical verification flow, also known as an in-design physical verification flow. This flow improves the overall turnaround time and ease of use of the physical verification process.
|Achieving Faster Time-to-Tapeout with In-Design Sign-Off Metal Fill |
Achieving correct-by-construction results during implementation significantly reduces time to tapeout and avoids schedule delays. This paper presents a pushbutton flow to generate timing-aware, signoff quality metal fill during place and route.
|Enhancing the DRC Waiver Methodology for Layout Verification Productivity|
To manage design violations, CAD departments have employed a number of solutions to reduce the amount of violations needed to be checked by the physical verification engineer. However, these solutions are limited.