IC Validator 

IC Validator is a complete physical verification tool, performing the increasingly complex DRC and LVS sign-off checks. In addition, it has been specifically architected for In-Design physical verification. In-Design physical verification means that the Place and Route engineers can run DRC and practical DFM steps alongside place and route within the familiar IC Compiler physical design environment.

The three cornerstones of IC Validator are

• High performance to run compute-intensive checks and DFM utilities, such as metal fills
• Foundry qualification for final signoff for DRC and LVS
• Seamless integration with Synopsys’ leading Place and Route solution, IC Compiler

Press Releases

• Achronix Tapes Out Industry's First FinFET-based System-on-Chip Using Synopsys' IC Compiler and IC Validator
• LG Adopts In-Design Physical Verification with IC Compiler and IC Validator after Multiple Successful Tapeouts
• Micronas Standardizes on Synopsys' Design and Verification Solutions for Automotive Designs
• UMC Adopts Synopsys IC Validator for Pattern Matching-Based Lithography Hot-Spot Verification at 28 nm
• Synopsys and TSMC Collaborate for 20nm Reference Flow
• 100 Tapeouts Underscore Rapid and Broad Acceptance of Synopsys In-Design Physical Verification
• Synopsys Delivers Design Enablement for TSMC 28-nm Process Technology

Product Information

• IC Validator Datasheet

White Papers

• IC Validator: Automatic DRC Repair
• IC Validator: GDS Merge
• IC Validator: Physical Verification for Analog Designs
• Achieving Faster Time-to-Tapeout with In-Design Sign-Off Metal Fill
• Enhancing the DRC Waiver Methodology for Layout Verification Productivity
• Accelerating Physical Verification with an In-Design Flow