Monday, June 4
11:30 a.m. to 1:30 p.m.
San Francisco Marriott Hotel
- You are doing bigger chips, faster chips — a key enabler is the move to 20nm. Are you wondering how your peers are managing the move to this node?
- What are their biggest challenges?
- How have they been addressed?
- What unknowns remain, what is yet to be solved?
- What are the drivers behind the move to 20nm – where is the biggest benefit?
Attend this luncheon seminar to learn from industry leaders who are blazing the trail!
Hear from experts in foundry, processor, wireless and consumer electronics companies, such as from GLOBALFOUNDRIES, Oracle, Samsung, STMicroelectronics who have successfully met the 20nm design enablement challenge with IC Compiler.
Who should attend?
Back-end, physical design engineers, project leaders and CAD team managers are the primary audience.
Attendance at this event is free, but registration is required. Seating is limited, so reserve your seat early.
|11:30 – 11:45 a.m.||Doors Open / Check In / Complimentary Lunch Served|
|11:45 – 12:00 a.m.||Welcome and Introduction by Synopsys|
|12:00 – 1:15 p.m.||Presentations by leading foundry, processor, wireless and consumer electronics companies|
|1:15 – 1:30 p.m.||Closing remarks and prize drawings|