IC Compiler II 

Hear what Designers are saying about IC Compiler II


Antun Domic Discusses IC Compiler II

IC Compiler II is a complete place and route system that enables 10X faster throughput for designs across all process nodes. Hear what Antun Domic, executive vice president and general manager of Synopsys' Design Group, has to say about this new physical implementation solution.

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IC Compiler II
IC Compiler II is a complete netlist to GDSII place-and-route system that enables 10X faster throughput for designs across all process nodes, while improving final quality of results (QoR). IC Compiler II is specifically designed to address today's hypersensitive time-to-market pressures while delivering best-in-class solutions for flat and hierarchical design planning, early design exploration and prototyping, placement and optimization, clock tree synthesis, routing, manufacturing compliance, and low-power challenges.

IC Compiler II Lunch and Learn

Achieving Industry-Best QoR on Advanced Designs

In this video, hear from industry leaders about how they are achieving success in their advanced designs using IC Compiler II technology to address physical design challenges and accelerate products to market.
HiSilicon, NVIDIA, Qualcomm, Socionext

IC Compiler II: Place and Route with the Power of 10X

At DAC 2015 in San Francisco, IC Compiler II was on display everywhere – in banners and jumbotron displays, at the Synopsys booth, in partner booth theatre presentations and most importantly at the IC Compiler II luncheon event at the Park Central Hotel. Over 300 luncheon participants stayed to hear each of five customers present their tapeout successes with IC Compiler II. These five customers are responsible for just a few of the nearly 100 tapeouts already achieved by IC Compiler II and clearly demonstrated place and route with the power of 10X.

IC Compiler II: Delivering the Power of 10X

At the 2015 Silicon Valley SNUG , IC Compiler II demonstrated both the realization and the continuing vision of the Power of 10X.
IC Compiler II activities this year included highlights in Aart’s keynote address, a lunch-and-learn panel of industry-leading customer presenters sharing their tapeout successes, and an R&D panel sharing the continuing vision and results, as well as tutorials for the overall design flow and new GUI of IC Compiler II. Experience IC Compiler II at SNUG 2015 through this short video.

R&D Insights

IC Compiler II Core Infrastructure
Mark Bales, Synopsys Scientist, explains the new IC Compiler II infrastructure and how it enables 10X faster throughput.

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IC Compiler II Optimization
Thomas Andersen, Group Director R&D, provides an overview of physical optimization in IC Compiler II and how the new global-analytics- based framework enables high QoR along with fast, hierarchical full chip closure.

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IC Compiler II Clock Synthesis
Aiqun Cao, Principal Engineer, discusses how IC Compiler II’s new clock synthesis delivers faster design convergence with automated variation-tolerance.

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IC Compiler II Design Planning
Neeraj Kaul, Group Director R&D, discusses hierarchical design planning in IC Compiler II and how the new data and tool architectures enable unprecedented design capacity and throughput.

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