Comprehensive Place and Route System
IC Compiler is an integral part of the Synopsys Galaxy™ Implementation Platform that delivers a comprehensive design solution, including synthesis, physical implementation, low-power design, and design for manufacturability. IC Compiler is a single, convergent, chip-level physical implementation tool that includes flat and hierarchical design planning, placement and optimization, clock tree synthesis, routing, manufacturability, and low-power capabilities that enable designers to implement today’s high-performance, complex designs on schedule.
IC Compiler is a comprehensive place-and-route system; it provides best QoR in timing, area, power, signal integrity, routability, out-of the-box results and faster design closure.
Multicore support throughout the flow delivers improved productivity. New technologies enable designers to handle gigascale, complex designs and meet tight project schedules.
IC Compiler is tightly correlated to the industry-standard signoff solutions – PrimeTime® SI and StarRC™. Additionally, it provides an optimal physical ECO implementation solution with PrimeTime ECO Guidance.
Growing design complexity, ever-increasing DRC rules and complex manufacturing compliance needs have rendered the prevailing implement-thenverify approach to physical verification suboptimal. In-Design technology made possible by the seamless integration of IC Validator DRC/LVS signoff solution and IC Compiler, allows designers to mitigate these challenges in the implementation stage for faster signoff closure.
IC Compiler provides a comprehensive manufacturability solution that concurrently optimizes for yield with timing, area, power, test, and routability. IC Compiler increases manufacturability of the design, optimizing both functional and parametric yield.
IC Compiler with concurrent hierarchical design enables powerful design planning and chiplevel feasibility, analysis features to handle large, complex designs. Providing early analysis and feasibility exploration, IC Compiler delivers smaller die size and achieves predictable design closure to reduce the cost of design.
IC Compiler with Zroute technology utilizes advanced routing algorithms, concurrent manufacturability optimizations and multi-threading, to improve manufacturability and deliver much faster turn-around-time.
IC Compiler with strong links to Design Compiler® Graphical, PrimeTime-SI, StarRC, IC Validator and PrimeRail faster design convergence and strong productivity benefits to all designers.
Figure 1: Synopsys Galaxy Implementation Platform
Innovative technology in IC Compiler delivers improved QoR, measured in terms of the complete cost vector – timing, area, power, signal integrity, routability, and manufacturability.
Concurrent multicorner multimode (MCMM) optimization across the flow, enhanced signal integrity capabilities, Multisource Clock Tree Synthesis (MSCTS) and physical datapath technology enable designers to meet aggressive QoR targets for gigascale, complex chips and high-performance cores at advanced technology nodes. “Physical Datapath” technology allows designers to create structures by specifying constraints for the relative column and row positions of instances. These structures are called relative placement (RP) structures. Figure 2 highlights some of the benefits of relative placement (RP).
Figure 2: Relative Placement (RP) reduces power and improves routability
IC Compiler provides the fastest path to results. This is achieved using best in-class placement, CTS and routing core engines, multicore support, powerful design planning capabilities, and complete convergence throughout the design stages, and faster design convergence with signoff accuracy.
Design Planning: IC Compiler includes complete flat and hierarchical design planning capabilities and delivers multi-million-instance design capacity. Because concurrent hierarchical design is native in IC Compiler, designers are able to concurrently carry out planning and implementation within a single environment, leveraging IC Compiler’s common engines, Tcl, GUI, and single timer from planning through physical implementation to tapeout. It is intended to be used for both a fast exploration of the design implementation solution space to minimize die size and to implement a final, optimized and detailed floorplan. Advanced optimization techniques in IC Compiler allow designers to implement the smallest routable die for their design while power network synthesis and analysis automatically creates a power network that meets IR drop requirements.
Figure 3: Thermal map based on PNS and IR drop
Correlation to Signoff: IC Compiler is tightly correlated to the industry-standard signoff tools, PrimeTime SI and StarRC. IC Compiler shares delay calculation modules with PrimeTime and PrimeTime SI, including cell delay, Arnoldi wire delay, Composite Current Source (CCS) models, as well as features like Clock Reconvergence Pessimism Removal (CRPR) and Advanced On-Chip Variation (AOCV) support for clock and data to achieve the highest correlation to signoff in the industry.
- Design Convergence: IC Compiler with links with other industry-standard Galaxy Implementation Platform tools facilitates faster design convergence. IC Compiler, in combination with Design Compiler Graphical, provides the strongest correlation between synthesis and physical implementation and helps minimize placement congestion. IC Compiler takes PrimeTime signoffdriven ECO guidance and implements it with minimum impact to layout and timing for faster ECO closure. In the final stages of design closure IC Compiler utilizes PrimeTime-SI; MCMM, MV aware guidance to incrementally deliver signoff assured design results. In-Design physical verification with IC Validator and IC Compiler provide signoff quality metal fill and DRC checking in the design stage. The In-Design flow also allows IC Compiler to automatically fix lithography hotspots detected by IC Validator. Lithography hotspot fixing provides faster design convergence (figure 4). In-Design static rail and EM analysis with PrimeRail and IC Compiler improves designer productivity.
Figure 4: Early analysis facilitates faster design convergence
Multi-Corner Multi-Mode (MCMM): Concurrent MCMM-aware placement, clock tree synthesis, routing, and optimization transformations dramatically reduce TAT for large, complex chips with multiple numbers of modes and corners. Intelligent optimization is driven by timing, area, power, signal integrity, routability and yield cost factors that are measured concurrently across all scenarios. The IC Compiler’s MCMM solution eliminates the ping-pong effects typically seen at later stages of the design flow.
Zroute Technology: Zroute technology in IC Compiler utilizes advanced routing algorithms and multi-threading capability to take full advantage of the multi-core compute platforms delivering much faster turn-around-time. The modern Zroute architecture incorporates state-of-the-art routing technology, such as native soft rules to enable litho-friendly routing and avoid manufacturing problems. Employing concurrent manufacturability optimization techniques, Zroute simultaneously considers the impact of manufacturing rules, redundant vias, timing and other design goals to deliver the highest QoR along with improved manufacturability.
Cost of Design
IC Compiler allows designers to utilize a variety of techniques to meet timing, power, area, routability and yield goals. This reduces the cost of design and increases predictability.
- Manufacturing Awareness: IC Compiler offers the only complete solution available to optimize for yield and manufacturability. Concurrent manufacturability optimizations reduce the number of remaining single vias, and the critical area for higher yield while still meeting timing QoR. Figure 5 highlights DRC repair with IC Compiler and In-Design physical verification.
- Power: Advanced multivoltage designs for wireless, mobile, and consumer applications must deliver maximum performance while minimizing power. Figure 6 shows the results of power-aware placement. IC Compiler and the Galaxy Implementation Platform support UPF (IEEE 1801) to deliver a complete lowpower flow to handle complex powersensitive designs.
- Design for Test (DFT): IC Compiler, as part of the Synopsys Galaxy Implementation Platform, provides a comprehensive test automation solution that offers system-onchip designers the fastest and most cost-effective path to highquality manufacturing tests and working silicon. Figure 7 shows IC Compiler scan chain reordering. Fully-integrated DFT MAX™, nextgeneration test compression and synthesis technology achieves high compression without affecting the test coverage, functionality, timing, or power requirements of the design.
Figure 5: IC Validator/IC Compiler can detect and fix DRC hot spots
Figure 6: Register grouping using power-aware placement reduces power
|Figure 7: Design before and after scan reordering|
Ease of Use
IC Compiler advances ease-of-use with intuitive commands to deliver best out-of-the-box results. The IC Compiler GUI provides user friendly and easy-to-use features that enable designers to resolve issues at all design stages. The GUI enables fast analysis, visualization, debugging and repair features. Figure 8 depicts the cross-highlighting debug features.
All of these shared technologies and key advances in IC Compiler enable the Synopsys Galaxy Implementation Platform to deliver the best QoR in terms of timing, area, power, routability, testability and manufacturability, as well as faster turnaround time and a predictable path to first-silicon success. Today, designers are using IC Compiler successfully to tape out complex, high-performance and lowpower designs at 40/28/20nm and below geometries.
Figure 8: Critical path cross-highlighting enables faster debugging
Multicore support for higher throughput for designs in mainstream silicon technologies
High performance for advanced silicon technologies
Comprehensive optimization capabilities meet timing, area, power, signal integrity, routability and manufacturing objectives
Predictability during the implementation process
Complete netlist-to-GDSII solution for best QoR and TTR
- Highly correlated with golden signoff solutions: PrimeTime SI and StarRC
- Shares common infrastructure and technologies with PrimeTime, such as Arnoldi, OCV, CRPR, CCS, common cell delay calculation and SDC constraints to ensure tight correlation
- Advanced On-Chip Variation (AOCV) support for clock and data improves TTR and eliminates extra margins
- Faster design closure by using signoff timing and extraction information
- In-Design physical verification with IC Validator and IC Compiler help achieve optimal metal fill and signoff quality DRC checking in the design stage
- Concurrent MCMM optimization through out the implementation flow
- Tight correlation with Design Compiler topographical technology
- Physical datapath enables dramatic improvement in productivity for datapath logic implementation and provides predictable results in timing, area, and power
- Faster top level closure with Transparent Interface Optimization
- Robust crosstalk flow during all stages; detects and fixes crosstalk violations
- Faster ECO flow with intelligent MCMM, MV aware PrimeTime-SI guidance for faster signoff
- Supports Unified Power Format (UPF - IEEE 1801) throughout the flow
- Support for multi-voltage designs during design planning, synthesis, placement, clock tree synthesis, routing, chip finishing and ECO stages
- Complete multi-voltage support
- Advanced algorithms deliver high-quality dynamic and leakage optimization results
- Power-aware placement technology groups registers to reduce dynamic power
- Support for complex clock gating in clock tree synthesis
- Low-power, SI-aware CTS
- Signal electromigration analysis and repair significantly improves design reliability
- In-Design static rail and EM analysis with PrimeRail and IC Compiler improves designer productivity
- Complete support for advanced design rules
- Soft rule support
- Cell and route-based yield optimizations
- Critical Area Analysis (CAA)
- Optimization of critical areas through wire-spreading/widening during global route, track assignment and detailed routing
- Automated, timing driven multipattern via selection
- Automated litho hotspot analysis and fixing for faster design convergence
- Timing-driven metal fill
- Staggered metal fill
- Litho-friendly routing
- Automated lithography hotspot fixing
- Faster In-design flow with IC Validator DRC/LVS signoff technology for accurate metal fill and automated DRC fixing
- Concurrent hierarchical design
- Complete design planning solution for hierarchical and flat designs
- Early analysis and feasibility exploration capabilities
- Multi-Million instance design capacity
- Complete multi-voltage flow with MTCMOS support
- Power network analysis (PNA), Power network synthesis (PNS), and powerpad synthesis capabilities
- Easier handling of complex P/G structures using template-based PNS
- Timing-driven automatic macro placement
- Improved floorplans with Data Flow Analyzer(DFA) capability
- Full Flip Chip design flow support
- Physically optimized scan chains deliver predictable timing closure
- Physical test-optimized flow with support for DFT Compiler and DFT MAX features using scanDEF interface
- Common engines throughout the flow
- Single timer
- Innovative optimization capabilities in timing, area, DFT, power, routability and manufacturability ensure best QoR
- Layer aware optimization
- Multisource CTS delivers better skew, and reduces OCV and power
- Robust clock mesh technology for very tight skew control
- Physical datapath delivers better QoR and predictability for effective datapath management in high speed designs
Clock mesh support to handle clock variations at advanced nodes
Ease of Use
- Tcl support throughout
- Advanced route editing features
- Powerful features enable design analysis, visualization, debugging, and fixing
- Cross-referencing between logic vs. physical analysis
- Clock tree synthesis skew and latency analysis
- Hierarchical clock tree browser
- Power Network Analysis (PNA)
- Visual maps for worst negative slack (WNS)/congestion/cell density/scan/ leakage power/dynamic power/total power and more
- Critical area analysis (CAA)
- Chemical mechanical polishing (CMP) thickness and hot spots
- Fast physical data analysis and editing
- PrimeTime-style analysis (path inspector)
- Library Interface
- Reads LIB synthesis library containing functionality, timing, and design rule constraints
- Reads Milkyway (MWY) physical library describing technology and cell outlines
- Reads LEF, technology file (TF) format
- Verilog netlist
- SDC, DEF, SPEF, SBPF
- Several user-level commands are provided for specifying and modifying the floorplan
- Verilog netlist
- SDC, DEF, SPEF, SBPF
- User Interfaces
- Tcl or GUI-based user interface
- All Design Compiler reports enhanced with physical information; additional reports and commands enable analyzing layout and checking consistency of libraries and input files
- SPARC Solaris (64)
- x86 Solaris (64)
- x86 Red Hat Enterprise (32)
- x86 Red Hat Enterprise (64)
- x86 SUSE Enterprise (32)
- x86 SUSE Enterprise (64)