IC Compiler 2009 Webinar Series  

Welcome to the IC Compiler 2009 Webinar Series  

These events were created to inform you on key technologies for speeding design closure. Check back to register for future events.

October 9
IC Compiler Ecosystem
There is a thriving ecosystem around IC Compiler and the Galaxy Platform products engineered to work together to speed design closure. Hear from designers who share how they have relied on the IC Compiler ecosystem to achieve faster time to results and improved productivity by attending this free webinar.
View Recording

June 25
Faster Power/Ground Grid Closure with In-Design Rail Analysis
Join our experts to learn how you can use in-design rail analysis to analyze and debug voltage drop, power up and electromigration (EM) effects as early as placement, helping you accelerate the path to final design closure.
View Recording     [ Download PDF]

June 9
Faster Design Closure with Congestion Minimization
This webinar will show you how predictable routing congestion from synthesis to tapeout eliminates unnecessary iterations, speeding up your overall turnaround time.
View Recording     [ Download PDF]

May 20
In-Design Physical Verification for Faster Time-to-Tapeout
Synopsys’ physical design and verification technologists will show you how the newly-announced (5/11/09) IC Validator, In-Design physical verification solution, combines timing awareness and signoff accuracy to speed up your tapeout schedule.
View Recording     [ Download PDF]

March 31
Accelerating Time-to-SI Closure
Attend this webinar to learn how to use signoff-driven SI-closure to keep your schedule on track and your performance on target.
View Recording    [ Download PDF ]

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