IC Compiler Webinar Series 2009 

In-Design Physical Verification for Faster Time-to-Tapeout 
View Recording

Please view our 45-minute webinar to learn from our technologists about the recently (May 2009) launched IC Validator, an ideal add-on to IC Compiler for In-Design physical verification. In-Design physical verification helps place and route engineers significantly reduce time to tapeout and improves DFM, by enabling physical verification within the implementation flow.

Overview:
Modifying your layout after implementation can affect other design targets such as timing, power and signal integrity. In-Design physical verification provides a push-button flow for signoff quality metal fill and Design Rule Checking (DRC) inside IC Compiler where timing can still be considered. Our physical design and verification technologists will show you how new IC Validator In-Design physical verification combines timing awareness and signoff accuracy to speed up your tapeout schedule.

Presenter:

Kerstin McKay

Kerstin McKay is CAE director for Synopsys’ Physical Verification products and has been with Synopsys since 2002. Kerstin received her Master of Science degree in Physics with Advanced Studies in Biomedical Engineering from the University of North Carolina at Chapel Hill.



Frank Tseng

Frank Tseng is R&D director for IC Compiler routing technology and has been with Synopsys since 2002. Frank received his Ph.D. degree in computer engineering from Syracuse University in 1996. Frank will be available to answer questions during the Q&A.

Back to IC Compiler Webinar Series



NewsArticlesWhite PapersWebinarsVideos