Overview: 
IC Compiler, a cornerstone of the Galaxy™ Implementation Platform, is today’s leading physical implementation solution. IC designers worldwide have standardized on IC Compiler and are using it to tape out their most challenging designs. There is a thriving ecosystem around IC Compiler and the Galaxy Platform products engineered to work together to speed design closure. The ecosystem areas covered in this event include signoff-driven SI closure with PrimeTime®, placement-congestion minimization with Design Compiler Graphical™, In-Design Rail Analysis™ with PrimeRail, and In-Design Physical Verification™ with IC Validator.

JC Lin

JC Lin is VP of Engineering at Synopsys. JC has been with Synopsys for more than 15 years working on various technologies, including RTL Synthesis and Physical Synthesis. Currently, JC leads the placement and clock tree synthesis (CTS) teams for IC Compiler. He holds a Ph.D. degree in Computer Science from State University at New York (SUNY) at Stony Brook.

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