32/28/20nm Webinar Series 

Welcome to the IC Compiler 32/28/20 nanometer Webinar Series 

As 32/28/20nm design challenges increase, we want to share input from others in the industry along with solutions available in IC Compiler and the Synopsys Galaxy platform. Join us for one or more of the following webinars. Check back to register for future events.

October 24
Addressing Challenges at 20nm: A Foundry and EDA perspective
Synopsys and Samsung jointly present some of the key challenges of designing and manufacturing at 20nm. Learn about solutions that address these challenges.
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October 13
28nm Silicon and Design Enablement – A Foundry and EDA Vendor Perspective
In this final webinar of the 32/28nm design series, Synopsys and GLOBALFOUNDRIES share their perspectives on 28nm process technology and design enablement and 32/28nm design solutions respectively.
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September 14
Fast Gold-Standard Extraction at 28nm with StarRC
Increasing design complexity and the impact of new parasitic effects make accuracy and productivity for IC design and signoff analysis even more challenging beyond the 28nm process node. In this webinar, Synopsys experts will discuss how StarRC addresses these advanced challenges at 28nm through silicon-accurate modeling and high-performance extraction, enabling SoC designers to achieve signoff with increased confidence.
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August 11
Manufacturing-Aware Routing at 32/28nm
With the advent of each new technology node the complexity of doing design has increased and the need to consider yield as one of the objectives during design is now considered a necessity at the 32/28nm node. In this webinar we will discuss how IC Compiler’s Zroute Technology is built to consider manufacturability as one of the objectives of routing along with the techniques to address manufacturing during routing.
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July 28
Realizing Today’s 32nm and Beyond Large Capacity Designs
Synopsys Design Planning R&D will highlight the latest hierarchical design exploration and planning technology available in IC Compiler for handling today’s large 32/28nm designs.
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June 9
Fastest Time to Tapeout with IC Validator
Design complexities at 32nm and below mandate a new approach to Physical Verification predicated upon a high-performance, hybrid signoff engine. IC Validator is a foundry-qualified signoff DRC/LVS tool which has been successfully deployed at leading IDMs and Fabless customers and was architected to eliminate late-stage surprises through In-Design Physical Verification with IC Compiler. This webinar highlights several high productivity IC Validator flows and features.
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