Reference Design Flow Features New Low Power and DFM Capabilities Based on Synopsys' Galaxy™ Design and Discovery ™ Verification Platforms
MOUNTAIN VIEW, Calif., and SHANGHAI, China–September 5, 2006--Synopsys, Inc. (Nasdaq: SNPS), a world leader in semiconductor design software, and Semiconductor Manufacturing International Corporation (SMIC--NYSE: SMI; SEHK: 0981.HK), the largest foundry in China, today announced that the two companies have jointly developed and deployed reference design flow 3.0. SMIC and Synopsys Professional Services worked together closely on the complete RTL-to-GDSII flow, which is based on the Synopsys Galaxy™ Design and Discovery™ Verification Platforms and SMIC's advanced 90-nanometer (nm) process. The proven flow incorporates a broad range of automated low-power and design-for-manufacturing (DFM) capabilities to help shorten time-to-market, reduce risk and ensure predictable success for complex system-on-chip (SoC) designs.
SMIC's low-power process and the reference design flow were validated using SMIC's multiple voltage standard cell libraries, low-power design kit, memory compiler and I/O. The flow features Synopsys' Galaxy Design Platform solutions for RTL synthesis and test, physical implementation and signoff. Advanced closure features in the flow target concurrent timing, power optimization and signoff, including signal integrity (SI) prevention, analysis and repair.
"SMIC's advanced 90-nm process demands a flow that addresses critical timing, power and DFM issues to reduce risk and shorten time to volume," said Paul Ouyang, vice president of Design Services at SMIC. "We worked closely with Synopsys and built on the success of our previous two reference design flows to deliver a proven path to silicon for our mutual customers. We look forward to an ongoing relationship with Synopsys as we move toward even more advanced process nodes."
The reference design flow 3.0 is derived from the design flow in Synopsys' Pilot Design Environment and can be extended and enhanced by designers to address design-specific requirements. Advanced hierarchical floor-planning capabilities in the flow support hard-macros and soft-macros. Advanced low-power capabilities include level shifter and isolation cell insertion, voltage area creation, multiple voltage power mesh creation, level shifter and isolation cell placement optimization, multiple voltage-aware CTS and multiple voltage-aware physical verification, which can reduce leakage power dissipation by 30 percent. All of these capabilities were validated using SMIC's low-power design kit, which consists of a level shifter, isolation cell and clock gating cell. DFM features include via optimization, as well as filler cell and filler cap insertion. Test capabilities in the flow reduce test data volume and time.
"Our close collaboration with SMIC has resulted in a flow that targets advanced deep-submicron process issues for the burgeoning Chinese market," said Rich Goldman, vice president of Strategic Market Development at Synopsys. "We continue to work closely with SMIC to deliver a fully validated flow that meets our end-customers' demanding design needs and helps them achieve predictable success for advanced SoCs."
Reference Design Flow 3.0 is available now. For more information, please contact your SMIC account manager or email: Design_Services@smics.com.
SMIC (NYSE: SMI; SEHK: 981) is one of the leading semiconductor foundries in the world and the largest and most advanced foundry in Mainland China, providing integrated circuit (IC) manufacturing service at 0.35mm to 90nm and finer line technologies. Headquartered in Shanghai, China, SMIC operates three 200mm fabs in Shanghai and one in Tianjin, and one 300mm fab in Beijing, the first of its kind in Mainland China. SMIC has customer service and marketing offices in the U.S., Italy, and Japan as well as a representative office in Hong Kong. For additional information, please visit http://www.smics.com.
Synopsys, Inc. (Nasdaq: SNPS) is a world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com.
Safe Harbor Statements
(Under the U.S. Private Securities Litigation Reform Act of 1995) Certain statements contained in this press release, such as statements regarding the ongoing collaboration between SMIC and Synopsys, may be viewed as "forward-looking statements" within the meaning of Section 27A of the U.S. Securities Act of 1933, as amended, and Section 21E of the U.S. Securities Exchange Act of 1934, as amended. Such forward-looking statements involve known and unknown risks, uncertainties and other factors (including without limitation the actual results of future collaboration between SMIC and Synopsys), which may cause actual events, and/or the actual performance, financial condition or results of operations of SMIC to be materially different from any future performance, financial condition or results of operations implied by such forward-looking statements. Further information regarding these risks, uncertainties and other factors is included in the Company's annual report on Form 20-F filed with the U.S. Securities and Exchange Commission (the "SEC") on June 29, 2006 and such other documents that SMIC may file with the SEC or The Stock Exchange of Hong Kong Limited from time to time.
Galaxy and Discovery are trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.