White Papers 

High Throughput GSPS Signal Processing Using Synthesizable IP Cores
This whitepaper illustrates how parallel processing synthesizable IP cores available in Synphony Model Compiler enable Giga Samples Per Second (GSPS) throughput on FPGAs, and efficient area/power trade-offs for ASIC targets. In particular, we demonstrate how Parallel FFT, FIR, and CIC blocks enable users to scale throughput beyond achievable clock frequencies, and/or reduce power with sub-linear increases in area.
Sunil Ashtaputre, Director of R&D, Synopsys; Baijayanta Ray, DSP IP Architect, Synopsys

My RTL is an Alien! - Automating ASIC to FPGA-Based Prototype Conversion
FPGA-based prototyping is gaining popularity because it provides an economical way to functionally verify an ASIC design by creating a prototype that runs close to "at speed." FPGA-based prototypes also provide a great platform for early system software development. However, FPGA architectures include resources, building blocks, power circuitry, and clocks that are fundamentally different from those of an ASIC. With over 70% of today's ASICs and systems-on-chips (SoCs) being prototyped in an FPGA, designers are looking for ways to ease the creation of FPGA-based prototypes directly from the ASIC design source files.
Angela Sutton, Staff Product Marketing Manager, Synopsys

10 Ways to Effectively Debug your FPGA Design
Today’s FPGAs implement the equivalent of millions of ASIC gates and continue to grow in size and complexity. With the increasing amount of time designers are spending debugging and diagnosing the design, there is a need both for better ways to find errors early and en masse, and for smarter techniques to isolate errors and apply incremental fixes. The newest generation of the Synplify Premier synthesis tool addresses these needs by supporting early design checks and hierarchical design approaches.
Angela Sutton, Staff Product Marketing Manager, Synopsys

FPGA Design Methods for Fast Turn Around
This white paper takes an in depth look at a variety of techniques to help you speed up your synthesis iterations. Whether the goal is aggressive performance or to get a working initial design or prototype on the board as quickly as possible, this paper provides information on traditional and new techniques that accelerate design and debug iterations.
Angela Sutton, Staff Product Marketing Manager, Synopsys

No Room for Error: Creating Highly Reliable, High-Availability FPGA Designs
Designers of FPGAs for military and aerospace applications need to increase the reliability and availability of their designs. This is particularly true in the case of mission-critical and safety-critical electronic systems. This paper provides brief definitions of key concepts: mission-critical, safety-critical, high-reliability, and high-availability. It then considers the various elements associated with the creation of high-reliability and high-availability FPGA designs including: FPGA design and verification flows, methodologies, processes and standards, architectural and algorithmic exploration, geographically distributed design teams, IP selection and verification, DO-254 compliance and much more.
Angela Sutton, Staff Product Marketing Manager, Synopsys

The Great Divide: Why Next-Generation FPGA Designs will be Hierarchical and Team-Based
Incorporating hierarchical team-based design is now seen as mission-critical to any company involved in the creation of one of today's high-end FPGA designs. This paper discusses the evolution of FPGAs and FPGA design, the concepts of top-down and divide-and-conquer design flows and the considerations and capabilities required to support true hierarchical team-based design along with content management and design reuse considerations.
Angela Sutton, Staff Product Marketing Manager, Synopsys

Fast, Efficient RTL Debug for Programmable Logic Designs
Today’s designers need an FPGA verification tool that allows them to quickly find and correct functional design errors in hardware at system speed. Download this paper to read about how Synopsys' Identify RTL Debugger stands alone as the tool providing the fastest design iterations and the most powerful features available for the debug of programmable logic designs. Download now.
Synopsys

Beyond Physical: Solving High-end FPGA Design Challenges
This paper examines the latest trends, tools and methodologies that you should consider before beginning your next FPGA project. Being aware of the issues and solutions will allow you to take full advantage of the vital resources and benefits offered by FPGAs and to navigate potential hurdles. Click here to register and download.
Angela Sutton, Staff Product Marketing Manager, Synopsys



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