|FPGA design for functional safety|
Using triple modular redundancy, error detection and correction, and ‘safe’ FSMs to ensure greater functional safety in FPGA-based designs
Jan 11, 2016
|Accelerated Synthesis Runtimes Increase Productivity|
As FPGAs grow ever bigger and more complex, hard-working synthesis tools are stepping up to help designers find optimum solutions for balancing runtime and quality of results.
Dec 17, 2015
|3 flavors of TMR for FPGA protection|
Back in the microprocessor stone age, government procurement agencies fell in love with the idea of radiation hardened parts that might survive catastrophic events.
Dec 10, 2015
|Beyond Debug - FPGAs for Fun and Prototyping|
Beyond Debug - FPGAs for Fun and Prototyping
Nov 20, 2015
|Why FPGA synthesis with Synplify is now faster|
The headline of the latest Synopsys press release drops quite a tease: the newest release of Synplify delivers up to 3x faster runtime performance in FPGA synthesis. In our briefing for this post, we uncovered the surprising reason why – and it’s not found in their press release.
Oct 23, 2015
|New FPGAs... From China?|
Gowin Debuts New FPGA Line
Aug 18, 2015
|Achieving Better Productivity with Faster Synthesis|
Using a feature-rich implementation tool helps designers focus on their own product differentiation while accelerating time to market and meeting cost targets.
Jun 23, 2015
|Eight tips for choosing your next FPGA tool|
FPGAs are increasingly being used as system accelerators and central processors as a quick way of improving system performance.
Jun 17, 2015
|Getting the most out of IP based FPGA design with Synplify|
How Synplify makes it easier to use IP in FPGA-based designs, and package your own IP for secure reuse, on Altera and Xilinx devices.
Feb 27, 2015
|Dealing with FPGA IP in all its forms|
More likely in the real world is the problem of FPGA IP in all its forms, some of which are packaged to work with your favorite FPGA platform, and some of which are not. There is always the choice to restrict IP selections to only compatible formats, but that may rule out otherwise acceptable code for an IP block that may in fact be a best-in-class solution.
Feb 12, 2015
|In FPGA design timing is everything, says Synopsys|
When your FPGA design fails to meet timing performance objectives, the cause may not be obvious. The solution lies not only in the FPGA implementation tools’ talent in optimising the design to meet timing, but also in the designer’s ability to specify goals upfront and diagnose and isolate timing problems downstream.
Designers now have access to certain tips and tricks that will help you set up clocks; correctly set timing constraints using tools like Synopsys Synplify Premier; and then tune parameters to meet the performance goals of your Xilinx FPGA design. - See more at: http://www.electronicsweekly.com/news/design/eda-and-ip/fpga-design-timing-everything-says-synopsys-2014-12/#sthash.Kgd9GbBl.dpuf
Dec 02, 2014
|Demonstrating ASIC IP performance and quality demands an FPGA-neutral design flow|
Companies designing new system-on-chip (SoC) products are subject to ongoing market pressure to do more with less and achieve higher returns. The result is shrinking engineering teams, reduced design tool budgets and shortened time lines to get new products to market.
Nov 14, 2014
|In FPGA Design, Timing is Everything|
This article explains how designers now have access to certain tips and tricks that will help them set up clocks; correctly set timing constraints using tools like Synopsys Synplify Premier; and then tune parameters to meet the performance goals of a Xilinx® FPGA design.
Jul 15, 2014
|Understanding QoR in FPGA Synthesis |
Getting better QoR depends on understanding what an FPGA synthesis tool is capable of, and how to leverage what it tells you. This article highlights how to achieve improved QoR using new Synplify Premier feature enhancements and methodology.
May 28, 2014
|How to Bring an SMC-Generated Peripheral w/AXI4-Lite Interface into the Xilinx Environment|
Synphony Model Compiler (SMC) is a model-based tool from Synopsys that synthesizes designs created in Simulink® and MATLAB® to generate optimized RTL for ASIC and FPGA targets. SMC includes a comprehensive high-level model library for creating math, signal-processing and communications designs in the Simulink environment. Using the included SMC Host Interface Block makes it simple to integrate a design you’ve created with the Synphony Model Compiler into a Xilinx embedded platform.
Jan 23, 2014
|Do you know how far you can trust your FPGA-based system?|
Radiation-induced single bit-flips can cause problems in FPGA-based designs, but using the FPGA fabrics and design synthesis for error detection and correction can improve resistance to soft errors.
Aug 20, 2013
|The fixed and the finite: QoR in FPGAs|
There is an intriguingly amorphous term in FPGA design circles lately: Quality of Results, or QoR. Fitting a design in an FPGA is just the start - is a design optimal in real estate, throughput, power consumption, and IP reuse? Paradoxically, as FPGAs get bigger and take on bigger signal processing problems, QoR has become a larger concern.
Jul 22, 2013
|Gigahertz FFT Rates on a 500MHz Budget|
Today’s systems often present a massive amount of very fast data at the front end that needs to be sampled and decimated quickly, typical of a system with a lot of data channels in play like satellite radio or cable head-end systems. Sample rates run into the gigahertz range, putting them outside the range of FPGA clock speeds if the constraint is one sample per clock. In this article, learn how Synopsys’ parallel FFT IP implementation allows data to be sampled and processed faster.
Apr 23, 2013
|Creating Highly Reliable FPGA Designs|
In this article, learn how Synopsys’ Synplify FPGA synthesis software can help engineers protect their FPGA designs from radiation-induced soft errors.
Mar 28, 2013
|Multi-Gigahertz FPGA Signal Processing|
Design teams from Xilinx and Synopsys know the importance of creating parallel architectures to accelerate signal processing applications on FPGA devices. In this article, learn how an FPGA clocked at 500MHz can support FFTs with gigasample per second data throughput rates.
Mar 28, 2013
|Power-Area Tradeoffs for Parallel Signal Processing Architectures|
Engineers working on datapath designs for high-speed signal processing must create architectures to meet the application’s performance and power needs. Learn how some of Synopsys’ signal processing flows can create and explore parallel architectures to address this challenge.
Mar 28, 2013
|Using Parallel FFT for Multigigahertz FPGA Signal Processing|
Very high-speed fast Fourier transform (FFT) cores are an essential requirement for any real-time spectral-monitoring system. As the demand for monitoring bandwidth grows in pace with the proliferation of wireless devices in different parts of the spectrum, these systems must convert time domain to spectrum ever more rapidly, necessitating faster FFT operations. This article examines the design of a parallel FFT (PFFT) with runtime-configurable transform length, taking note of the throughput and utilization numbers that are achievable when using parallel FFT.
Feb 01, 2013
|Bugs Be Gone! Smarter debug and synthesis techniques to get your FPGA design to work on the board|
The article highlights Synopsys FPGA software differentiators available to help customers determine what to do when the design won't synthesize completely, and describes how to shorten debug times in order to get the design working on the board sooner.
Oct 31, 2012
|Next-Generation Xilinx FPGA Flows|
This article explains how Synopsys' Synplify FPGA synthesis tools complement Xilinx's new VivadoTM Design Suite for designers seeking more capacity and shorter turnaround times from their FPGA design flows.
Aug 12, 2012