Synphony Model Compiler 

High-Level Synthesis with Synphony Model Compiler 

high-level synthesis flow with Synphony Model Compiler
Figure 1: Synphony Model Compiler provides a faster, more automated path from
high-level algorithm descriptions to FPGA or ASIC, prototypes, and verification flows.

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Faster and More Efficient Model Creation
Modeling environments are popular for algorithm design and exploration because they allow concise representations of behavior at very high levels of abstraction. These environments provide sophisticated design capture, simulation and analysis tools for multiple domains. However, problems arise when the designer needs to translate the design intent into their RTL counterparts for use with ASIC or FPGA implementation tools. In particular, traditional methods have proven to be very time consuming and/or prone to error because of re-coding and re-verification into the RTL domain. The Synphony Model Compiler high-level synthesis solution addresses these problems by providing an easy and automated method to synthesize electronic system-level algorithmic representations from the Simulink / MATLAB model-based design environment.

Optimizations, Exploration, and Verification from a Single Model
Synphony Model Compiler enables rapid exploration of architectural tradeoffs from a single model and reduces errors and risk by maintaining consistent verification across multiple architecture choices and target technologies. Given the user-specified target and architectural constraints, the high-level synthesis (HLS) engine automatically optimizes at multiple levels by applying pipelining, scheduling, and binding optimizations across the entire system, including IP blocks and throughout the design hierarchy. Synphony Model Compiler also includes advanced technology characterizations that utilize Synplify Premier or Design Compiler for FPGA or ASIC respectively. This provides the accurate timing estimation needed to make device-specific optimizations across FPGA and ASIC targets. More importantly, it increases the reliability of verification through these design project phases, regardless whether the target is for FPGA-based prototyping, fast architecture exploration, or ASIC implementation.

C-Output for Earlier Software Development and Faster System Validation
The difficult and time consuming effort of creating models for system validation and functional verification is a major challenge in today's system modeling and verification environments. Synphony Model Compiler addresses this challenge by combining its highly efficient modeling flow with C-Output model generation. In addition to optimized RTL, the high-level synthesis engine generates flexible, high performance fixed-point ANSI-C models that can be used in virtual prototypes for early software development and a variety of other system simulation environments.

Synphony Model Compiler brings these capabilities together for the first time in a single environment that supports complete, integrated solutions with Synopsys' FPGA design, ASIC implementation, and FPGA-based prototyping verification flows.

Improved Reliability and Time to Market
The benefits of Synphony Model Compiler are the ability to validate algorithm concepts much earlier in the design cycle, catch functional and system-level problems much earlier, and more rapidly explore design space tradeoffs. With a more automated flow from higher levels of abstraction, Synphony Model Compiler gives system and algorithm designers much more power to realize these benefits and significantly improve the reliability and time- to-market of their ASIC and FPGA projects.

Synthesizable fixed-point high-level IP model library
  • Eliminates writing of fixed-point models from scratch
  • Faster verification at higher levels of abstraction
  • Offers more control over results
High-Level Synthesis Optimizations and Transformations
  • Automatic system-wide pipeline insertion scheduling and resource sharing
  • IP-aware micro architecture optimization
  • Automatic retiming and pipelining at the architecture level
  • Automatic scheduling for area optimization
  • Target-aware optimization for FPGAs and ASICs
Integrated ASIC Flow
  • Automatic generation of RTL constraints and scripts for Design Complier
  • Advanced timing estimation using Design Compiler
  • Rapid architecture exploration of speed, area and power tradeoffs
Integrated FPGA Flow
  • Automatic generation of RTL constraints and scripts for Synplify Pro / Synplify Premier
  • Advanced timing estimation using Synplify Pro / Synplify Premier
  • Optimized resource mapping to advanced FPGA devices such as hardware multipliers, MACS, adders, memories and shift registers
RTL Testbench Generation
  • Automatic generation of text vectors and scripts for RTL verification in VCS
C-model Generation for Software Development and System Validation
  • Fast model creation for C-based verification
  • Begin software development earlier using virtual prototypes

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