Synopsys’ FPGA design solution is a comprehensive suite of FPGA implementation and debug tools that deliver the industry’s best quality of results for both timing performance and area optimization. Fast synthesis algorithms, along with multi-processing, hierarchical and incremental design technologies, deliver the accelerated timing closure and time-to-market that is required for today’s complex FPGA designs. Integrated debug technology allows designers to work directly in their RTL code making it much more productive and intuitive than the typical method of debugging synthesized gates. As soft errors such as Single Event Upsets (SEUs) resulting from atmospheric radiation have become more common at ground level, applications involving human safety increasingly require SEU mitigation techniques. Synopsys has automated technologies to both detect and correct such soft errors in FPGAs. Synopsys FPGA solution is technology and vendor independent, allowing designers to quickly retarget from one FPGA vendor device to another from a common, easy to use, environment.
To learn more about Synopsys’ FPGA design tools, read the whitepapers or download a FREE evaluation of Synplify.Compare Synthesis Product Features
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