Overview
Are your FPGA projects taking too long? Now that FPGA devices have grown into hugely capable Programmable SoC’s in their own right, are your design methods struggling to keep up?
If you answered yes to any of these questions then join the experts from the Synplicity Business Group for this half-day technical seminar on Advanced FPGA Design and Verification, where you will learn how to adopt more powerful, more productive and more predictable FPGA design and verification techniques, whether you use FPGA in your final product or for ASIC prototyping.
- Attendees will learn how Synopsys tools provide:
- Model-based algorithmic design
- IP integration
- Tightly coupled constraint and analysis environments
- Integrated synthesis and placement
- ASIC-like RTL Verification for FPGA
- On-board assertion-based verification linked to RTL simulation
Agenda
| 9:00 - 9:30 | Arrival and registration | | 9:30 – 9:50 | FPGA at Synopsys: Introducing the Synplicity Business Group. Traversing the ASIC-FPGA intersection | | 9:30 – 9:50 | Achieving Peak Results: Timing Constraints and Analysis. Design Optimization and Advanced Analysis | | 10:50 – 11:20 | Break | | 11:30 – 12:00 | Predictable Timing Closure: Physical Synthesis and Analysis | | 12:00 – 1:00 | Advanced Verification Techniques: Directed Testing, Constrained Random Verification | | 1:00 – 1:10 | Wrap-up and Final Questions |
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We are keeping this seminar short so that you can quickly learn how Synopsys’ FPGA Technology can help with your current and/or future designs with as little impact on your projects and budgets as possible.
Schedule:
North America:| Date | Location | Registration | | June 2 | Columbia, MD | CLOSED | | June 3 | Schaumburg, IL | CLOSED | | June 3 | Manhattan Beach, CA | CLOSED |
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Please bookmark this site and check back often as it will be updated as seminar details and registration information become available.