|Getting the most out of IP based FPGA design with Synplify|
How Synplify makes it easier to use IP in FPGA-based designs, and package your own IP for secure reuse, on Altera and Xilinx devices.
Feb 27, 2015
|Dealing with FPGA IP in all its forms|
More likely in the real world is the problem of FPGA IP in all its forms, some of which are packaged to work with your favorite FPGA platform, and some of which are not. There is always the choice to restrict IP selections to only compatible formats, but that may rule out otherwise acceptable code for an IP block that may in fact be a best-in-class solution.
Feb 12, 2015
|In FPGA design timing is everything, says Synopsys|
When your FPGA design fails to meet timing performance objectives, the cause may not be obvious. The solution lies not only in the FPGA implementation tools’ talent in optimising the design to meet timing, but also in the designer’s ability to specify goals upfront and diagnose and isolate timing problems downstream.
Designers now have access to certain tips and tricks that will help you set up clocks; correctly set timing constraints using tools like Synopsys Synplify Premier; and then tune parameters to meet the performance goals of your Xilinx FPGA design. - See more at: http://www.electronicsweekly.com/news/design/eda-and-ip/fpga-design-timing-everything-says-synopsys-2014-12/#sthash.Kgd9GbBl.dpuf
Dec 02, 2014
|Demonstrating ASIC IP performance and quality demands an FPGA-neutral design flow|
Companies designing new system-on-chip (SoC) products are subject to ongoing market pressure to do more with less and achieve higher returns. The result is shrinking engineering teams, reduced design tool budgets and shortened time lines to get new products to market.
Nov 14, 2014
|In FPGA Design, Timing is Everything|
This article explains how designers now have access to certain tips and tricks that will help them set up clocks; correctly set timing constraints using tools like Synopsys Synplify Premier; and then tune parameters to meet the performance goals of a Xilinx® FPGA design.
Jul 15, 2014
|Understanding QoR in FPGA Synthesis |
Getting better QoR depends on understanding what an FPGA synthesis tool is capable of, and how to leverage what it tells you. This article highlights how to achieve improved QoR using new Synplify Premier feature enhancements and methodology.
May 28, 2014
|How to Bring an SMC-Generated Peripheral w/AXI4-Lite Interface into the Xilinx Environment|
Synphony Model Compiler (SMC) is a model-based tool from Synopsys that synthesizes designs created in Simulink® and MATLAB® to generate optimized RTL for ASIC and FPGA targets. SMC includes a comprehensive high-level model library for creating math, signal-processing and communications designs in the Simulink environment. Using the included SMC Host Interface Block makes it simple to integrate a design you’ve created with the Synphony Model Compiler into a Xilinx embedded platform.
Jan 23, 2014
|Do you know how far you can trust your FPGA-based system?|
Radiation-induced single bit-flips can cause problems in FPGA-based designs, but using the FPGA fabrics and design synthesis for error detection and correction can improve resistance to soft errors.
Aug 20, 2013
|The fixed and the finite: QoR in FPGAs|
There is an intriguingly amorphous term in FPGA design circles lately: Quality of Results, or QoR. Fitting a design in an FPGA is just the start - is a design optimal in real estate, throughput, power consumption, and IP reuse? Paradoxically, as FPGAs get bigger and take on bigger signal processing problems, QoR has become a larger concern.
Jul 22, 2013
|Gigahertz FFT Rates on a 500MHz Budget|
Today’s systems often present a massive amount of very fast data at the front end that needs to be sampled and decimated quickly, typical of a system with a lot of data channels in play like satellite radio or cable head-end systems. Sample rates run into the gigahertz range, putting them outside the range of FPGA clock speeds if the constraint is one sample per clock. In this article, learn how Synopsys’ parallel FFT IP implementation allows data to be sampled and processed faster.
Apr 23, 2013
|Creating Highly Reliable FPGA Designs|
In this article, learn how Synopsys’ Synplify FPGA synthesis software can help engineers protect their FPGA designs from radiation-induced soft errors.
Mar 28, 2013
|Multi-Gigahertz FPGA Signal Processing|
Design teams from Xilinx and Synopsys know the importance of creating parallel architectures to accelerate signal processing applications on FPGA devices. In this article, learn how an FPGA clocked at 500MHz can support FFTs with gigasample per second data throughput rates.
Mar 28, 2013
|Power-Area Tradeoffs for Parallel Signal Processing Architectures|
Engineers working on datapath designs for high-speed signal processing must create architectures to meet the application’s performance and power needs. Learn how some of Synopsys’ signal processing flows can create and explore parallel architectures to address this challenge.
Mar 28, 2013
|Using Parallel FFT for Multigigahertz FPGA Signal Processing|
Very high-speed fast Fourier transform (FFT) cores are an essential requirement for any real-time spectral-monitoring system. As the demand for monitoring bandwidth grows in pace with the proliferation of wireless devices in different parts of the spectrum, these systems must convert time domain to spectrum ever more rapidly, necessitating faster FFT operations. This article examines the design of a parallel FFT (PFFT) with runtime-configurable transform length, taking note of the throughput and utilization numbers that are achievable when using parallel FFT.
Feb 01, 2013
|Bugs Be Gone! Smarter debug and synthesis techniques to get your FPGA design to work on the board|
The article highlights Synopsys FPGA software differentiators available to help customers determine what to do when the design won't synthesize completely, and describes how to shorten debug times in order to get the design working on the board sooner.
Oct 31, 2012
|Next-Generation Xilinx FPGA Flows|
This article explains how Synopsys' Synplify FPGA synthesis tools complement Xilinx's new VivadoTM Design Suite for designers seeking more capacity and shorter turnaround times from their FPGA design flows.
Aug 12, 2012
|Time is Money! A quick fix for those pesky FPGA design errors|
This article discusses the newest generation of FPGA design tools and how they are responding to the complexity of FPGAs and multi-FPGA systems by supporting hierarchical design approaches.
May 05, 2012
|Completing Hardware Innovation Cycles in Less than Six Months: An Internet Data Center Server Case Study|
Pressures to deliver next-generation products to market, without compromising quality, are fundamentally changing the way designers create products. Many are architecting their products with change and the need for quick upgrades in mind. FPGA-based prototyping is an attractive option that provides quick feedback on the operation of the design. This article discusses how companies like SeaMicro utilize FPGA-specific synthesis tools to generate ASIC prototypes efficiently and with the required performance.
May 04, 2012
|FPGA Design: From Top-down to Bottom-up|
This article discusses why the ability to use hierarchical team-based design is now seen as being mission-critical by any company involved in the creation of one of today’s high-end FPGA designs, making true hierarchical team-based design one of the most requested features of FPGA tool providers.
Jun 03, 2011
|Better FPGAs, Sooner|
This articles describes methodologies to help you minimize runtime through a mixed top-down, bottom-up design approach and other techniques to achieve faster turnaround for your FPGA based flow. These techniques can help you achieve twice as many design iterations per day, better results stability from one run to the next when you make small changes, and faster feedback on other changes you make to your design.
May 12, 2011
|How big did you say that FPGA is?|
In this article, Jeff Garrison, Director of FPGA Implementation Marketing, discusses the need for new team-design capabilities, such as mixed top-down and bottom-up flows, distributed development methodologies, faster tool iterations and advanced project reporting at the sub-block and top-level of the design.
Sep 20, 2010
|Automating the FPGA Design Debug Process|
As FPGAs grow more capable, they will increasingly replace ASIC devices for certain applications where bleeding-edge performance or extremely large volumes are not required. And as the prevalence of FPGAs as integral components of products continue to increase, debugging of these large devices will only grow more arduous. These trends will render already antiquated gate-level debugging techniques totally obsolete. Only with more advanced debugging tools will we be able to meet next-generation time-to-market demands. This article, by Jeff Garrison, Director of Product Marketing FPGA Synthesis tools, discusses the challenges of debugging large FPGA devices and provides insight into the tools and methodologies that alleviate some of these challenges.
Jan 19, 2010
|How to achieve timing-closure in high-end FPGAs|
Timing-closure is a growing concern for FPGA designers, particularly with the recent introduction of multi-million gate architectures fabricated at the 90 nm and 65 nm technology nodes.
Jan 23, 2008