Synplify Feature Comparison Chart 

 
Synplify Feature Comparison Chart
Synplify®Synplify Pro®Synplify® PremierCertify®
Design Flow Automation and Customization
Integration with FPGA vendor place & route and embedded system tools (EDK, SoPC Builder)
TCL scripting to drive custom flows and custom reports
Batch mode (floating/ network licenses only)
Management of multiple design implementations for larger team-oriented design projects
Best Quality of Results
Customized mapping software for each FPGA device family ensures optimal implementation and technology independence
Automatic memory and DSP inferencing provides implementation of a design with optimal area, power and timing quality of results
Timing knowledge of Altera megafunctions and Xilinx COREGen modules enables system-level optimizations
Integrated SynCore module generation for high-performing, area-efficient implementations of arithmetic/datapath functions from FPGA vendor-independent RTL
FSM extraction, optimization and debug, with user control
Enhanced logic synthesis to improve timing results
Faster Turnaround Times and Board Bring-Up
Incremental block-based and design preservation flows for consistent results
Automatic compile points incremental flow, for up to 4x faster runtime while maintaining QoR

Incremental static timing analysis

Continue-upon-error mode to reduce iterations required for board bring-up, by identifying multiple errors in one synthesis run

Up to 10x runtime increase using fast synthesis mode multiprocessing with automatic compile points

Hierarchical "Divide-and-Conquer" Flows for Faster Turnaround and Design Preservation
Hierarchical bottom-up flows

Mix and match bottom-up and top-down flows

Hierarchical reporting

Synchronization of geographically distributed / multi-machine parallel projects

Hierarchical Process Management Interface to monitor design progress and errors

Broad Language and Device Support
VHDL, Verilog, SystemVerilog, VHDL 2008

Support for devices from all FPGA vendors: Achronix, Altera, Lattice, Microsemi (formerly Actel) and Xilinx

Mixed language synthesis

Advanced Design Debug and Diagnosis
Integrated language-sensitive HDL source code editor with syntax checker

Interactive HDL Analyst Tool for fast isolation of performance and functional problems

Option

Divide-and-conquer hierarchical debug and bug isolation flows

Debug Design Operating on the Board from your RTL (Identify RTL Debugger)
Pinpoint and monitor operation on design nodes and conditions of interest by defining watch points and sophisticated trigger conditions

Automatic compilation and insertion of debug logic into the FPGA implementation

Incremental debug and fix-up

Automated Design for High Reliability and Safety-Critical Design Including DO-254
Repeatable synthesis results

Traceable and verifiable flows using controls that limit synthesis optimizations and that maintain critical logic and nodes within the design

Fault-tolerant FSM implementation (Hamming-3)

Automatic inference of error-correcting memories

Triple modular redundancy (TMR) with voting logic

Safe finite state machines (FSM) implementation and control with custom error detection and mitigation

Advanced FPGA-Based Prototyping Support and Easy ASIC Code Retargeting to FPGA
ASIC tool RTL language and SDC constraints compatibility

Automated gated clock conversion

Netlist editor and compiler constraints feature streamlines ASIC design import and retargeting

HAPS prototyping system integration

DesignWare IP integration and optimization

Integration with VCS Simulator for simulation data analysis

FPGA DesignWare IP support Synchronized with your ASIC
Complete DesignWare Library Building Block IP integration

Synopsys coreTools integration, for FPGA designs that include DesignWare digital cores

Advanced Power Optimization and Estimation
Generate high-quality switching data to drive power optimizations

Automated power conservation for unused RAM blocks

Automatic power optimization of Xilinx DSP48 primitives

Convert ASICs into Multi-FPGA Prototypes
Automated and manual design partitioning

Muti-chip FPGA debug provides seamless visibility across devices

Design planning and impact analysis helps determine feasible design fit across multiple FPGAs

Synthesis & FPGA project encapsulation manages multiple FPGA projects and automates processing steps

Synopsys HAPS Support
HAPS Aware hardware query and validation eases initial system bring-up
Accurate prototype performance viewing using multi-chip, system-level static timing analysis
Complete library of HAPS motherboard and daughter board descriptions
Clock synchronization methodology and IP eases ASIC clock conversion to FPGA-based resources and avoids clocking errors
High-Speed Time Domain Multiplexing (HSTDM) I/O sharing maximizes FPGA interconnection bandwidth
Automates chaining of UMRBus connections throughout the prototype DUT
Apply HAPS SRAM Daughter Boards for high-capacity debug storage expands signal visibility and sample period
Supports integration of Accellera-standard SCE-MI and AMBA transactor library IP via HAPS-60 Co-Sim & TBV Suite



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