Overview
Synopsys Synplify Pro® and Synplify Premier® synthesis tools, the preferred solutions for complex FPGA design, have been enhanced to handle the most demanding design challenges and provide the best quality of results. The software's highly automated multiprocessing, fast synthesis mode and incremental flows allow designers to focus on differentiating their own products while meeting schedule and cost targets. View Synplify Premier and Synplify Pro features side by side in the Synplify Feature Comparison Chart.
New features in the 2011.09 software release include:
- Enhanced debug visibility within the synthesis interface to help eliminate design flaws via simulation and RTL debug of the design on the board
- New capabilities that better automate creation of designs requiring highly reliable operation and error recovery in the field
- Hierarchical design flow enhancements to centrally monitor status, debug and track results and make autonomous progress on individual design modules
- The only DesignWare® IP FPGA solution that is fully synchronized with ASIC flows, now additionally enhanced to support DesignWare Library MacroCells
New Features and Benefits
Automated hierarchical design flows for parallel development, design reuse, and merging and results stability
With production FPGAs now larger than 10M equivalent ASIC gates, designs are increasingly being developed using a hierarchical methodology, often by multiple team members who are globally distributed. Enhancements to the tools' hierarchical design flow, first introduced a year ago to support parallel or distributed design development, include an interface that displays and verifies synthesis settings prior to synthesis to avoid user errors. The interface also enables designers to centrally monitor their designs by tracking subproject status as each part of the design is synthesized and completed, as well as navigate and explore the hierarchy of area and timing results reports and messages. ASIC designers who are prototyping their design in an FPGA can take advantage of this hierarchical flow for the most challenging designs, including those that include ASIC-gated and ASIC-generated clocks that cross hierarchical boundaries in the FPGA prototype. The hierarchical design interface offers designers the flexibility of using bottom-up flows, top-down flows or a combination of the two without requiring any floorplanning. This facilitates modular design and reuse of internally developed IP and even allows the design to proceed before the RTL for all of the design blocks is available.
Highly reliable operation that is resistant to single event upsets
Designers of system-critical applications are becoming increasingly concerned about radiation-induced errors, or Single Event Transients (SETs). SETs, when clocked into a sequential element, can lead to Single Event Upsets (SEUs) and cause a critical design failure. Synplify Premier now gives designers the ability to build SEU-resistance directly into the design. Designers can instruct the synthesis tool to automatically create and preserve sequential logic, including safe FSMs, as specified in the RTL, for the specific purposes of error detection and recovery.
Eliminate design flaws by visualizing and diagnosing simulated results or actual design operation on the board
Designers can visually observe whether the design is likely to operate as intended. Simulation data for the design, generated using Synopsys' VCS Simulation tool can be superimposed directly on top of the synthesis tool's netlist-level schematic allowing the design's operation to be related directly back to the design specification and the design implementation for quick validation. Additionally, by running the Identify RTL debugger included in Synplify Premier, designers can now view data values from the design operating on the board. The data is directly superimposed on the RTL-level schematic, either for a particular error or at the moment in time when a particular operating condition of interest occurred. The designer sets watch points and complex trigger conditions within the Identify debugger to pinpoint specific data and observe specific conditions of interest. This new capability allows the designer to debug the design when an error is observed, relating the error manifestation back to the RTL specification. The capability also enables the designer to confirm that their design is operating as intended.
Synplify Premier - VCS and Identify Integration
Visualization & Selection of VCD Data in HDL Analyst
The only integrated FPGA-independent IP solution
Further enhancing the DesignWare® Library building block integration into the Synplify Premier tool, it can now synthesize DesignWare MacroCell Infrastructure IP, including DWC AMBA™ (AXI™, AHB™, APB™), APB advanced peripherals, APB peripherals, microcontrollers (DW8051, DW6811) and memory controller components. The encrypted RTL cores that are configured and generated using Synopsys coreConsultant utility can now be used by both FPGA and ASIC flows. The very same RTL that includes DesignWare component instantiations can be used by Design Compiler, VCS and Primetime to synthesize and verify an ASIC implementation, and can then be used by Synplify Premier to synthesize an FPGA-based prototype of the ASIC.
Find out more...
- Synplify Premier Brochure
- Hierarchical Team Design White Paper
- Mil-Aero Solution Brochure
- High Reliability White Paper
Request Synplify Premier Evaluation