High-Reliability Design: No Room for Error 

Achieve Functional Safety and Highly Reliable Design 

Synopsys offers FPGA designers a high-reliability solution to help create products that are resistant to radiation-induced errors, single bit glitches and require high up-times, such as those in industrial, medical, automotive, communications, military and aerospace applications.

Industry standards including DO-254, IEC 61508 and ISO 26262 define functional safety and error mitigation strategies for the creation and validation of high reliability systems. The Synplify® Premier tool automates proven methods for mitigating soft errors such as single-event upsets (SEUs) that are increasingly present in the latest FPGA process geometries. Synplify Premier provides two essential elements to automate SEU immunity and create safe designs that operate with high reliability in radiation-rich environments.

  • Direct support for SEU error detection and recovery schemes across all FPGA device families from Altera, Lattice, Microsemi and Xilinx
  • Automated support for the creation of SEU error monitors, enabling software-based error mitigation schemes for controlling, monitoring, recovery and diagnostics of system errors due to SEUs

Synplify Premier provides designers an automated methodology for the integration of triple modular redundancy, memory on I/O protection and safe and fault tolerant finite state machines. Triple modular redundancy (TMR) corrects single bit errors by triplicating a circuit and then adds in "voting" logic to determine the best two out of three results. There are several methods for implementing TMR, giving designers multiple options to consider for each design.

  • Local TMR protects registers
  • Distributed TMR protects synchronous logic or external I/Os
  • Block TMR protects synchronous modules, IP, routing and clocks

High-Reliability Design

TMR helps mitigate SEUs induced by radiation effects by inserting redundancy during synthesis with triplicated circuitry + voting logic

Premier synthesis takes special care to mitigate errors in non-flushable circuits that contain synchronous feedback loops and allows for can physical separation of the triplicates on the FPGA die for additional SEU protection. In addition to TMR support, there is integrated support for several other error mitigation techniques.

  • Memory protection by inferring error correcting code (ECC) memory primitives and by inserting TMR on Block RAMs to mitigate single-bit errors.
  • Safe FSM implementation that will force a state machine into a reset state or into a user-defined error state so the error can be handled in a specific way. The software can implement a “safe case FSM” which will ensure that, should the FSM enters an undefined state, it will recover, avoiding state machine lock-up.
  • Fault-tolerant FSMs with Hamming-3 encoding for detecting and correcting single-bit errors, thus allowing correct operation of the FSM to resume right away.

Once an error is detected, an error flag is required to signal the error condition to the system software. The creation of these error flags is automated for a given design and developers can then tap these flags from any node on the die and from ECC RAMs error flag pins. In addition to TMR, which can be used to create error flags, Synplify Premier can generate “Duplicate with Compare” circuitry which employs a dual-mode redundancy scheme followed by a comparator circuit to create an ERROR_FLAG signal that alerts the presence of an SEU in order to trigger corrective operation, such as memory scrubbing

High-Reliability Design

Duplicate-with-compare circuitry can be used to flag errors or to trigger custom error mitigation or scrubbing

Learn more about creating highly reliable designs with Synplify Premier:

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