The widespread use of custom circuits in today’s advanced system-on-chip designs is creating a severe design and simulation bottleneck. Increasing complexity combined with the modeling of new parasitic effects are exacerbating the accuracy concerns as well as resulting in 2-4x increase in simulation runtimes. In this webinar, our experts will explain how StarRC Custom’s unique solution enables high accuracy and optimized extraction for improved simulation throughput. Technologies that will be demonstrated include unified 3D field solver, context-specific MOS device parasitic extraction, CustomSim simulation efficiency links and OpenAccess based integration with the Galaxy Custom Designer implementation solution.
Baribrata Biswas, Group Director, R&D / Extraction , Synopsys Inc.; Omar Shah, CAE / Extraction, Synopsys Inc.
Nov 11, 2009

Analog/RF design solution helps meet design challenges
Christopher Labrecque, HSPICE Marketing Manager, and Fredrik Ivarsson, Custom Design Corporate Applications Engineer
Nov 04, 2009

Follow the front-to-back development of an AMS block using Synopsys' Galaxy Custom Designer implementation solution.
Joe Mastroianni, VP of R&D, Les Spruiell, Product Marketing Manager, and Chris Shaw, Technical Marketing Manager
Nov 03, 2009

In this webinar you will learn how CustomSim addresses verification challenges for a diverse array of functional blocks, including custom digital, analog and memory designs. Learn how to take advantage of multi-threading capabilities to achieve an additional 4x performance improvement. Increase design confidence by finding electrical rule violations and power management failures rapidly with a comprehensive set of static and dynamic native circuit checks.
Synopsys
Apr 28, 2009