Verification 

High-Performance, Scalable SoC Hardware and Software Verification 

Synopsys Verification Continuum™ is a comprehensive verification platform built from the industry’s fastest engines for virtual prototyping, static and formal verification, simulation, emulation, FPGA-based prototyping and debug. Verification Continuum features Unified Compile based on VCS® for a simulation-like use model throughout the verification flow, enabling faster design bring-up, seamless transitions between simulation, emulation and prototyping. It also delivers Unified Debug with Verdi® to provide a debug continuum across all domains and abstraction levels enabling dramatic increases in debug efficiency. Verification Continuum is architected for scalable FPGA-based emulation and prototyping systems with the multi-megahertz speed needed for early software-development and SoC verification.

 

 
Synopsys' virtual prototyping solution includes the Virtualizer tool set and the industry's largest portfolio of transaction-level models.


VC CDC
Next-generation CDC static checking solution
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VC LP
Advanced Low Power static checking solution
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HECTOR
Next-generation formal block-level consistency checker


Formal Equivalence Checking
Comprehensive equivalence checking


VC Formal Coverage Analyzer
Integrated formal analysis for coverage closure



VCS
High-performance verification, new multicore technology


VCS AMS
Mixed-signal verification solution


Verification IP
Synopsys Verification IP Protocols


VC Formal
Next-generation formal verification solution
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VC CDC
Next-generation CDC static checking solution
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VC LP
Advanced low power static rules checker solution
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VCS NLP with MVSIM
Voltage-aware native low power simulation
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VC Formal Coverage Analyzer
Integrated formal analysis for coverage closure



Certitude
Functional qualification system
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ZeBu Emulation
Billion-gate ASIC and SoC acceleration and emulation


Leda
Static checker


Verification Compiler
Comprehensive, best-in-class verification in one product
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Magellan
Formal hybrid verification


Pioneer-NTB
SystemVerilog testbench with Vera testbench automation


VCS AMS
Mixed-signal verification solution


CustomSim
Unified circuit simulation solution for nanometer designs


CustomSim Circuit Check
Increase verification coverage and discover trouble spots


CustomSim Reliability Analysis
Transistor-level reliability analysis


FineSim
Full-chip circuit-level simulation


HSPICE
Gold standard for accurate circuit simulation


CustomExplorer
Transistor-level debugging environment


Custom WaveView
Post-simulation, high-performance AMS waveform analyzer


CustomExplorer Ultra
Regression & Analysis Environment for Mixed-signal Verification


Mixed-Signal Simulation
Highest-throughput mixed-signal simulation

  • Debug
  • Open debug solutions for design and verificationmore

Verdi
Automated debug system
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Siloti
Visibility automation system
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ProtoLink
Probe visualizer
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VIP that accelerates run-time, debug and coverage closure for SoC designs


 
High-performance SoC emulation systems help engineers find hardware and embedded software bugs fast, shortening time-to-silicon


 
Improves time-to-market and helps avoid costly device re-spins by enabling early embedded software development and allowing HW/SW co-design well ahead of chip fabrication.

Key Benefits
  • Industry’s fastest engines for virtual prototyping, static and formal verification, simulation, emulation, FPGA-based prototyping and debug
  • Unified Compile with VCS for a simulator-like use model throughout the verification flow
  • Unified Debug with Verdi with a consistent debug user experience across multiple engines for 3X productivity
  • Architected to support high-performance, scalable FPGA-based emulation and prototyping systems

Verification Challenges
Mobile and Internet of Things (IoT) markets are driving dramatic increases in SoC complexity and software content, and intensifying pressure on time-to-market. To address these challenges, SoC teams require many verification technologies such as simulation, emulation and prototyping across the spectrum of pre-silicon verification, post-silicon validation and software bring-up. Today, it takes months of design bring-up and transition effort between disjoint technologies, further complicated by the need to debug across domains and to support large software teams.

Leading teams are adopting "shift-left" strategies with concurrent practices across pre-silicon verification, post-silicon validation and software bring-up to SoC shorten time-to-market. Synopsys’ Verification Continuum enables these shift-left strategies with best-in-class verification technologies unified with seamless design bring-up, transition and debug throughout the flow.



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