White Papers 



HDMI2.0a Verification IP
HDMI (High-Definition Multimedia Interface) is a proprietary audio/video interface for transferring uncompressed video data and compressed or uncompressed digital audio data from an HDMI-compliant source device, such as a display controller, to a compatible computer monitor, video projector, digital television, or digital audio device. HDMI is a digital replacement for analog video standards, represented using one of several luminance/color-difference color spaces.
Snigdha Arora, Synopsys

SoundWire Test Suite
Often Verification IP and design integration require in-depth understanding of the protocol and methodology. This requires significant investment of time in building the expertise in-house. To accelerate the process for our customers, Synopsys’ Soundwire VIP solution is written in 100% native SystemVerilog to enable ease-of-use, ease-of integration and high performance.
Jitendra Singh Kushwaha, Synopsys

Demystifying the HDCP2.2 Authentication Process
This paper explains HDCP2.2 which is the latest generation content protection protocol. Our primary focus here is to explain how the authentication process on HDCP2.2, the various steps that are necessary in able to validate the receiver. The encryption on the keys in version 2.2 is more advanced than previous versions (HDCP1.X), which basically makes it harder to break. HDCP 2.2 is required for 4K Ultra HD images by the Consumer Electronics Association (CEA) which makes it even more important now.
Rishabh Mishra, Synopsys

Digital Audio Simplified: MIPI SoundWire
MIPI Alliance has come up with a new protocol standard for sound interface called SoundWire. SoundWire is a robust, scalable, low complexity, low power, low latency, two-pin (clock and data) multi-drop bus that allows for the transfer of multiple audio streams and embedded control/commands. To understand its specification and design verification needs, it is important to understand basics of digital audio transmission. This paper explains the common digital audio formats, PCM and PDM, which are target applications for MIPI Soundwire.
Jitendra Singh Kushwaha, Synopsys

Extending Digital Verification Techniques for Mixed-Signal SoCs with VCS AMS
The VCS AMS mixed-signal verification solution extends proven digital verification techniques to mixed-signal designs to deliver high-quality verification coverage of complex mixed-signal SoCs.
Helene Thibieroz, Adiel Khan, Dave Cronauer, Synopsys

Five Vital Steps to a Robust Testbench with VC Verification IP and UVM
This white paper explains how to start performing constrained random verification quickly and easily using Universal Verification Methodology (UVM) based VC verification IP (VIP). A few benefits of VC VIP with UVM are described here, followed by an introduction to UVM. This supplies a background for the discussion of the five initial steps to coding a complete constrained random testbench. The concepts and techniques used in this paper are explained and demonstrated, and code examples are provided to show real application of the techniques.
Amit Sharma, Synopsys

VC VIP: A New Generation of Verification IP
The role of verification intellectual property (VIP) has become increasingly important over recent years as a vital component in achieving SoC verification productivity and is now fully established as an essential part of any verification solution. As the number of protocols and their complexity has increased, the demands on verification engineers to achieve productive verification and debug has also increased. This white paper discusses the limitations of first-generation verification IP and explains how VC VIP addresses these challenges.
Neill Mullinger, Synopsys

Rethinking SoC Verification
The industry is at an inflection point that calls for new, integrated verification solutions that will offer a fundamental shift forward in productivity, performance, capacity and functionality. Synopsys is meeting this demand with Verification Compiler™. Verification Compiler provides the software capabilities, technology, methodologies and VIP required for the functional verification of advanced SoC designs in one solution.
Rebecca Lipon, Synopsys

Transaction Debug with Verdi
SoC design is complex. It involves both software and hardware design that calls for a higher level of abstraction to ensure accurate verification. Transaction-level verification and debug offers this higher abstraction, while staying close to actual hardware signals. Traditionally, its use has been limited by the lack of a better mechanism and database to capture the critical information needed to do transaction debug, and a better way to view transaction data once captured. Through transaction debug, Verdi now enables users to maintain both the higher level of abstraction of a software debug environment with a direct connection to hardware signal data, thereby correlating their software and hardware debug approaches.
Rich Chang, Synopsys

Enabling Synchronized Hardware Software Debug with Verdi³
Verdi³™ HW SW Debug is an instruction-accurate embedded processor debug solution that offers fully synchronized views between hardware, as RTL or gate-level design models, and software, as C or assembly code — enabling co-debug between RTL and software.
Alex Wakefield, Synopsys; Joerg Richter, Synopsys

MOS Device Aging Analysis with HSPICE and CustomSim
MOS Reliability Analysis (MOSRA) in HSPICE and CustomSim offers a robust and economic alternative to empirical overdesign and extensive lifetime testing.
Bogdan Tudor, Joddy Wang, Weidong Liu, Hany Elhak, Synopsys

Using Digital Verification Techniques on Mixed-signal SoCs with CustomSim and VCS
A case study that explains the various aspects of a scalable and reusable methodology for verifying analog IP that can be applied to VMM/UVM, from verification planning to testbench implementation and coverage collection.
Graeme Nunn, Calvatec; Fabien Delguste, Adiel Khan, Abhisek Verma, Bradley Geden, Synopsys

Accelerating Analog Simulation with HSPICE Precision Parallel Technology
HSPICE Precision Parallel technology is a new multicore transient simulation extension to HSPICE for both pre- and post-layout of complex analog circuits such as PLLs, ADCs, DACs, SERDES, and other full mixed-signal circuits. HPP addresses the traditional bottleneck in accelerating SPICE on multicore CPUs with new algorithms that enable a larger percentage of the simulation to be parallelized, with no compromise in golden HSPICE accuracy. Additionally, efficient memory management allows simulation of post-layout circuits larger than 10 million elements.
Robert Daniels, Sr. Staff Engineer, Synopsys Inc.; Harald Von Sosen, Principal Engineer, Synopsys Inc.; Hany Elhak, Product Marketing Manager, Synopsys Inc.

Advanced Verification IP Accelerates PCIe Integration Test
PCI Express is an excellent example of where design reuse and adoption has become the norm for design teams, so while the verification teams are no longer faced with full compliance testing they are still challenged with validating that the PCI Express (PCIe) design IP is functioning correctly in the context of the SoC. Clearly, this has a major effect on the verification effort. After all, the verification teams working on integration test shouldn't need to worry about compliance; that should have been taken care of by the IP provider's extensive verification, certification and wide usage in the industry. This whitepaper gives a few pointers on what should be included in integration test and how to get it done efficiently.
Neill Mullinger, Synopsys

Ten Things You Should Know About Verification IP
This fact sheet discusses how to select verification IP (VIP) to maximize your productivity. So, you have chosen to look a little deeper into the benefits of commercial VIP. This is the first step on a path to more productive and complete SoC and IP verification: buying VIP instead of building your own avoids a slew of VIP development, quality and support headaches. Now you need to select a VIP vendor and this can be a critical choice. While you will certainly benefit from using commercial VIP, not all VIP are created equal and some will benefit you much more than others. So, how do you figure out a VIP that maximizes your productivity.
Neill Mullinger, Synopsys

Verifying Cache Coherency Protocols with Verification IP
The use of on-chip cache memory helps design teams optimize multicore designs for both power and performance. Synopsys' SystemVerilog-based VIP suite and Reference Verification Platform provides comprehensive support for AMBA ACE cache coherency, which enables design teams to accelerate the verification of complex multicore SoCs that take advantage of the ACE protocol. The verification suite provides native support for UVM, VMM, and OVM, and includes comprehensive support for generating stimulus sequences as well as automatic built-in checks, coverage and debug capabilities.
Synopsys

The Shifting Landscape of SoC Verification
The next major shift in verification technology will bring about an order-of-magnitude increase in productivity, which will help design teams to address the rising cost of verification.
Michael Sanie, Synopsys

Discovery Verification IP
New Generation of VIP to Address the Growing Challenge of Complex Protocol and SoC Verification.
Neill Mullinger, Synopsys

Solving Modern Verification Challenges
As industry leaders typically are the first to tackle design complexity issues, it is imperative that they deploy a verification solution that they can rely on to meet all of the verification challenges inherent to modern chip design. This white paper outines these verification challenges and the requirements of a verification solution that successfully addresses them.
Michael Sanie, Badri Gopalan, Synopsys

Solving Graphics IC Verification Challenges
Successful, on-time delivery of graphics ICs places tremendous pressure on the required verification process and solution. This whitepaper briefly describes the challenges faced when verifying graphics ICs, the requirements for verification solutions that meet those specific challenges and innovative technologies and capabilities offered by VCS.
Michael Sanie, Badri Gopalan, Synopsys

Solving Networking IC Verification Challenges
Successful, on-time delivery of networking ICs places tremendous pressure on the required verification process and solution. This whitepaper briefly describes the challenges faced when verifying networking ICs, the requirements for verification solutions that meet those specific challenges and innovative technologies and capabilities offered by VCS.
Michael Sanie, Badri Gopalan, Synopsys

Solving Processor IC Verification Challenges
Successful, on-time delivery of processors places tremendous pressure on the required verification process and solution. This whitepaper briefly describes the challenges faced when verifying processors, the requirements for verification solutions that meet those specific challenges and innovative technologies and capabilities offered by VCS.
Michael Sanie, Badri Gopalan, Synopsys

Solving SoC Verification Challenges
Successful, on-time delivery of processors places tremendous pressure on the required verification process and solution. This whitepaper briefly describes the challenges faced when verifying processors, the requirements for verification solutions that meet those specific challenges and innovative technologies and capabilities offered by VCS.
Michael Sanie, Badri Gopalan, Synopsys

High-performance, Parallel Simulation with VCS Multicore Technology
This white paper provides a detailed overview of VCS multicore technology, which improves verification performance by taking advantage of advances in the compute infrastructure. VCS multicore technology cuts verification time in half by harnessing the power of modern multicore CPUs and allows designers to identify performance bottlenecks and distribute time-consuming activities across multiple cores for faster functional verification and debug. Automatic partitioning and load balancing, event synchronization and memory optimization make VCS multicore unique for high-performance functional verification. Multicore technology combines the speed-up from parallel computation with the industry-leading Native Testbench (NTB) compiler optimization technique to deliver unmatched verification performance for large-scale designs for chip-level and system-level verification.
Usha Gaira and Sanjay Sawant




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