White Papers 

Low Power Verification for Multi-rail Cells
Multi-voltage designs have become increasingly common in order to achieve low power. Multiple supply rails are an essential part of multi-voltage designs. Assuming that all output pins in a logic cone are related to a single supply voltage can cause functional failures in silicon or excessive power loss. Consequently, verification tools need to understand the relationship between the driving voltage rails and the impact on each output pin to accurately resolve the logic values. Synopsys’ Eclypse solution provides an infrastructure to capture the necessary information and MVSIM and MVRC are able to use the information to accurately verify multi-rail designs and lead to silicon success. This white paper discusses the challenges faced with static and dynamic verification of multi-rail cells in the context of low power designs.
Prapanna Tiwari, Synopsys, Inc.

Decoupling Capacitance Estimation, Implementation and Verification: A Practical Approach for Deep Submicron SoCs
The problem of dynamic variations in supply voltage and the related impact on chip performance is a major issue facing today's DSM SoC design teams.
David Stringfellow John Pedicone

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