Videos 


VMM-LP Tutorial Video

Power management and low power design bring a whole new assortment of bugs and failure mechanisms to IC designs. The task of verification, already a critical path in the delivery of the chip, now needs to take on additional tests and flows to ensure that the power management scheme is functional. In this tutorial, our panelists focus on the need for a rigorous low power verification methodology and the ways in which the Verification Methodology Manual for Low Power can help you achieve comprehensive verification of increasingly complex low power designs.
Brian Dickman, Director of Design Assurance, ARM Srikanth Jadcherla, Group Director of R&D, Synopsys Janick Bergeron, Fellow, Synopsys



DAC 2009: Coping with Modern AMS Challenges

The guest panel of industry experts discussed how they are addressing key verification challenges at 32 nanometers, achieving high-accuracy verification for complex BCD and FPGA applications, and using power management techniques for custom DSP designs.
John Chilton, Sr. VP of Marketing & Corporate Development, Synopsys; Aaron Barker, Staff Engineer, Sun Microsystems; Eugene Chen, CAD Director, Alter; Sandeep Tare, Verification Methodology Engineer, Texas Instruments; Lyes Djama, Smart Power Design Flows Manager; Pierluigi Daglio, AMS Design & Verification Flows Manager, STMicroelectronics



DAC 2009: Solutions for Tough Verification Challenges

Synopsys hosted a special VCS Verification Luncheon event at DAC in San Francisco, CA focused on the VCS functional verification solution. Verification R&D experts from leading companies discussed how they leverage VCS’s multicore performance, transaction-based verification, tight mixed-signal integration, comprehensive low power verification capabilities and proven methodologies to solve today’s toughest verification challenges.
John Chilton, Sr. VP of Marketing & Corporate Development, Synopsys; YC Wong, Director of IC Engineering, Broadcom; Shrenik Mehta, Sr. Director of Frontend Tools and OpenSPARC, Sun Microsystems; Faisal Haque, Director of Engineering, Qualcomm; and Amit Chowdhry, Member of Technical Staff, AMD



The Unique Challenge of Low Power Verification

With over 30 industry experts contributing to the book, the methodology documented in the VMM-LP is based on real-life design.
Janick Bergeron, Fellow in the Verification Group



The Birth of the VMM-LP

In this video you will hear how the VMM-LP came to be and how it addresses the challenges of low power verification.
Srikanth Jadcherla, Group R&D Director in the Verification Group



How Does the VMM-LP Benefit the Industry?

Hear about some of the potential problems of low power verification and how the VMM-LP helps overcome them.
David Flynn, Fellow at ARM



VMM User Forum Lunch Event: ARM, Ltd.

Need for a Low Power Verification Methodology. Learn about ARM and Synopsys’ joint efforts to develop a Verification Methodology for Low Power Designs.
Alan Hunter, Verification Methodology Lead

PDF DOWNLOAD PRESENTATION (PDF)



VMM User Forum Lunch Event: Renesas Technology Corporation

Low Power Verification User Experience See a presentation on the unique challenges of low power design verification and how they are being addressed by Reneses using Synopsys' tools.
Yoshio Inoue, Chief Engineer

PDF DOWNLOAD PRESENTATION (PDF)



VMM User Forum Lunch Event: NVIDIA

Engineering the APX2500: Verification Methodology for Low Power Watch a presentation on NVIDIA’s experience using the Verification Methodology for Low Power Design on the APX2500, the world’s lowest power, high definition video and graphics computer on a chip.
Soma Bhattacharjee, Director of Engineering

PDF DOWNLOAD PRESENTATION (PDF)



VMM User Forum Lunch Event: IBM

"Are We There Yet?" Listen to a discussion on VMM Planner and how IBM used it on their BIST project to determine when they had run enough random tests.
Nancy Pratt, BIST Verification Lead

PDF DOWNLOAD PRESENTATION (PDF)



Eclypse Low Power Solution

Josefina Hobbs introduces the Eclypse Low Power Solution
Joselina Hobbs



Design and Verification of Ultra Low Power SoCs with ARM Cores

This presentation describes the common challenges and solutions in the design and verification of SoCs striving for power and performance efficiency. In particular, we discuss how ARM's IEM technology can control power and performance, focusing on the integration of ARM cores, IEM technology, and the process of architecting and verifying a low power scheme using these components. We also provide guidance in the hardware and software partitioning of low power schemes.
Srikanth Jadcherla, Group Director of R&D, Synopsys -- Prapanna Tiwari, Manager, Corporate Applications Engineer, Synopsys


Power Management Demo

Synopsys is the world leader in design software for SoCs and electronic systems. The company sells its products to semiconductor, computer, communications, consumer electronics, aerospace and other companies that develop electronic products.
Synopsys




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