|May 28, 2014||Synopsys Bridges Design and Verification with Next-Generation Static and Formal Technology for Verification Compiler|
Synopsys announces the availability of its VC Formal comprehensive formal verification solution, and VC CDC and VC LP advanced static checking solutions. These solutions address the growing verification challenges of complex SoCs by introducing next-generation verification technology that finds bugs earlier, faster and more accurately, as well as accelerates root-cause analysis.
|Jan 25, 2010||Toshiba Information Systems (Japan) Standardizes on VMM-LP Low Power Verification Methodology|
VMM-LP Enables Structured Deployment of Low Power Verification Technologies
|Jul 01, 2009||Synopsys MVSIM Adopted for Low Power Verification of STw8500 Mobile SoC Platform|
Comprehensive Support for Low Power Techniques and High Level of Accuracy Significantly Improve Bug Detection. Synopsys, Inc. today announced that ST-Ericsson has adopted Synopsys' MVSIM low power dynamic verification solution for its STw8500 system-on-chip (SoC) platform for the mobile phone market. ST-Ericsson selected MVSIM for its proven ability to comprehensively verify low power techniques, including standby and built-in automated low power assertions, which enable the early detection of bugs.
|Apr 06, 2009||Synopsys Delivers 2x Verification Speed-up with VCS Multicore Technology|
MOUNTAIN VIEW, Calif., April 6 /PRNewswire-FirstCall/ -- Synopsys, Inc. , a world leader in software and IP for semiconductor design and manufacturing, today unveiled new multicore technology within the VCS® functional verification solution, a key component of Synopsys' Discovery™ Verification Platform.
|Apr 06, 2009||Synopsys Unveils CustomSim Unified Circuit Simulation Solution|
MOUNTAIN VIEW, Calif., April 6 /PRNewswire-FirstCall/ -- Synopsys, today announced its new CustomSim™ circuit simulation solution. The best-in-class simulation technologies of NanoSim®, HSIM® and XA have been unified into a single circuit simulation solution with added multicore capabilities delivering up to four times (4x) performance improvement for large analog and mixed-signal circuits.
|Apr 06, 2009||Synopsys Introduces Discovery 2009 Delivering Faster, Unified Verification Solutions|
MOUNTAIN VIEW, Calif., April 6 /PRNewswire-FirstCall/ -- Synopsys, today introduced the latest generation of its Discovery™ Verification Platform, an integrated verification solution for analog/mixed-signal (AMS) and digital designs. Discovery 2009 delivers unprecedented verification productivity with new multicore simulation technologies, native design checks and comprehensive low power verification capabilities throughout the platform.
|Jun 03, 2008||ARM, Renesas Technology and Synopsys Define Industry's First Low-Power Verification Methodology|
Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced that it has collaborated with ARM and Renesas Technology to define the industry's first methodology to address the rapidly increasing complexity of low power verification.
|Feb 25, 2008||Synopsys Introduces the Eclypse Low Power Solution|
Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced the Synopsys Eclypse™ Low Power Solution, the industry's most comprehensive suite of proven system-level, verification, implementation and signoff tools, intellectual property (IP), methodologies and services for low power chip development.
|Jun 18, 2007||Synopsys Acquires ArchPro Design Automation|
Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, today announced that it has acquired ArchPro Design Automation Inc. ArchPro's technologies enable engineers to address power management challenges in multi- voltage designs from chip architecture to RTL and gate-level design.
|Mar 29, 2007||Synopsys Accelerates Low Power Designs With Comprhensive Implementation and Verification Solution|
Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, today announced that it is enhancing its comprehensive low-power verification and implementation solution to ensure compliance with the widely supported Unified Power Format (UPF) 1.0 Accellera standard.