Adoption of low power design techniques is growing rapidly to enable ASICs and SoCs to support the advanced power management required across today's electronic products, from mobile devices to servers and networking. Advanced low power techniques such as Power Gating, Retention, Low-Vdd Standby, and Dynamic Voltage Scaling (DVS) employ voltage control to enable fine-grained power management. Designs are partitioned into power domains that can be separately controlled by one or more of these low power design techniques. Increasingly stringent power requirements have necessitated the use of multiple supply voltages. Low power designs typically operate in different modes, with each mode corresponding to one or more power states. Comprehensive verification of low power designs requires verification not just in all the power states, but also of the specified transitions and transition sequencing between power states as the design moves from one operating mode to another. A single bug in any of these incredibly complex scenarios may cause functional failures in silicon.
- Download Datasheet
Simulation Challenges for Low Power Designs
It is no longer sufficient to simulate a design assuming voltage to be a constant. Most designs today have voltage changes during operation, such as when a design enters a low-Vdd standby state or utilizes DVS modes. This requires simulation to understand voltage levels to accurately resolve signal values and timing. Power state transitions require understanding of the dynamic nature of voltage and its effect on logic; outputs become a function of not only the logical value on the inputs, but also the voltage levels of those values. Traditional ("always-on") simulations will produce inaccurate and misleading results, potentially allowing bugs to escape and manifest in silicon.
In addition, multi-voltage designs have design components operating under different supply voltages from multiple supply rails. Traditional simulators don't have the intelligence to understand the relationship between different supply voltages and what they drive, causing potential silicon failures that go undetected in simulation.
Power-on resets for low power designs involve turning power domains on in a strictly-defined sequence, where a powered-up domain may subsequently help power up the next domain. Understanding the voltage transitions and dependencies during power-on reset is essential to accurately and completely verify a low power design.
VCS with MVSIM Native Low Power ("NLP") Mode
MVSIM equips VCS® to natively perform voltage-level aware simulation with a complete understanding of the UPF-defined power network, including at RTL prior to implementation flows. This uniquely allows engineers to comprehensively verify correct behavior of designs that use advanced voltage control techniques for power management, and catch potentially design-killing low power bugs very early in the design process.
- Key Features and Benefits
- Catch LP bugs early and quickly with accurate simulation of designs using advanced low power techniques, including Power Gating and Retention
- Voltage-level aware simulation accurately verifies designs with Low-Vdd Standby and DVS
- Infrastructure to model and correctly simulate Multi-Rail macros leads to increased bug detection for multi-voltage designs
- Built-in, automated assertions derived from analysis of the design and power intent mitigate the risk of undetected bugs and increase verification productivity
- Automated coverage tracking and reporting helps track verification
- Production-proven support for industry-standard IEEE 1801-2009 [Unified Power Format (UPF)] power intent format
VCS Native Low Power Flow
VCS with MVSIM takes in the same Verilog or VHDL RTL or gate-level netlist representation of the design as in standard flows, and accepts the same testbench as in standard flows (optionally augmented for low power checks). However, the native low power flow requires power intent to be specified in an UPF-format file, which is loaded into VCS with the design and the testbench. MVSIM equips VCS to read this UPF, model the entire power network described in the UPF, and accurately understand the low power policies and voltage events. VCS in native low power mode will output a log file and an error and warnings report for all violations related to multi-voltage checks. (MVSIM standalone continues to support legacy PLI flows for VCS and 3rd party simulators)
Figure 1: Low power simulation flow
- Unique Value of VCS NLP
- Voltage-level aware simulation detects bugs when multiple voltages transition simulataneously in a design, or as a result of incorrect operation during a voltage ramping up or down. Voltage-level awareness helps verify the complex power-on-reset protocols found in low power designs.
- Comprehensive verification of voltage-control techniques, such as Low-Vdd Standby and DVS, that involves voltage value resolutions which can only be done by voltage-aware simulation
- Ability to associate different power domains with different supply voltages allows for accurate simulation of multi-voltage designs
- Built-in automated assertions, based on years of low power verification expertise, is transparently available in VCS native low power flows. The rich set of low power assertions is generated based on the design and power intent and helps pin-point complex bugs. This feature augments manual assertion generation, which can be error-prone and tedious.
Adoption of advanced low power design techniques is growing rapidly. Multi-voltage designs require comprehensive verification coverage of all voltage-control techniques. VCS native low power with MVSIM delivers voltage-level aware simulation that accurately understands voltage values and covers all power states, transitions and sequences. VCS with MVSIM is production-proven and widely adopted at leading systems and semiconductor companies.