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Have You Really Verified Your Multi-rail, Low Power Design?
Low power designers have adopted increasingly aggressive techniques such as using multiple supply voltages. Multiple supply voltages imply a design with blocks and cells featuring multiple supply rails, further compounding the already daunting task of verifying low power designs. Incomplete or improper verification of such designs leaves open the possibility of functional failures in silicon.
Apr 06, 2010

Low-Power Design Portal Serializes VMM-LP Chapters
The Low-Power Design Portal has published serialized installments of Chapters 5 and 6 of the Verification Methodology Manual for Low Power (VMM-LP).
Feb 24, 2010

Why Voltage-aware Verification Strategy Counts
Verification of low-power designs, which until recently was a challenge for just a handful of all designs, is fast becoming every designer's problem.
Nov 25, 2009

Power and Verification Always Matter
EDACafé reviews the Verification Methodology Manual for Low Power (VMM-LP).
Jun 25, 2009

Chip-verification and -design flow focuses on low power
The latest generation of Synopsys’ Discovery verification platform upgrades the offering with new multicore simulation technologies, native design checks and low- power verification capabilities.
May 01, 2009

Verification Methodology for Low Power: Your Blueprint to Working Silicon
The widespread design of energy-efficient mobile devices, desire for green power, and government regulations on idle power have created a powerful market force for the pervasive employment of design techniques for reducing power.
Apr 10, 2009

Synopsys Introduces Discovery 2009
Platform Encompasses New Multicore Simulation Performance, Native Design Checks, Comprehensive Low Power Verification Capabilities, and CustomSim Unified Circuit Simulation Solution.
Apr 06, 2009

Synopsys Moves Tools to Multicore Hosts
Synopsys has increased verification speed and brought digital, analogue and memory simulation under the same roof as it moves its tools to multi-core hosts.
Apr 06, 2009

Boost verification accuracy with low-power assertions
Low-power designs have raised the bar on the verification effort. Designs optimized for power often employ complex design techniques that introduce their fair share of new bugs that are hard to track and fix.
Jul 28, 2008

Powered Down
Just about every analysis of chip design claims verification consumes more than half of the time needed today to bring a semiconductor system to market.
Jun 22, 2008

A Ticking Time Bomb
Power is a hot problem these days, no pun intended. To address the escalating power challenges, many companies have adopted multi-voltage design techniques such as power gating, back bias, multi-VDD, dynamic voltage frequency scaling (DVFS), and retention.
Jun 09, 2008

Coding Practices Adapt to a Low-Power World
For many years, good coding practices have been an essential component of design methodology. Register-transfer-level (RTL) structures have been known to cause unintended bugs as well as DFT, power, clock-structure, and sometimes even place-and-route issues.
Jun 01, 2008




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