Finding a hardware bug in the middle of a multi-billion-cycle test requires more than just dumping RTL waveforms in and around an assertion or logic analyzer trigger point. At the SoC system-level, full-chip waveform generation from the emulator isn't scalable or practical—there's simply too much data.
Typical emulation tests may run for hours or days between bugs being observed, and the problem may be manifested anywhere within the billions of cycles of testing. ZeBu's "smart" debugging methodology leverages advanced technology at multiple levels of abstraction to help you converge on the relevant location and timing of an error:
- software debugger integration
- transaction logging and transactor packet/frame analyzers
- trace memory & logic analyzers
- SystemVerilog Assertion support and coverage reporting
- Fast Waveform Capture to assist the developer in identifying the cycle and functional area of the failure.
Once a failure has been isolated to a practical window, ZeBu’s interactive Combinational Signal Analysis (iCSA) with native Verdi integration delivers on-the-fly 100% design accessibility and scalable RTL waveform generation.
Hardware debugging in a software context can be complicated by its asynchronous nature. When stepping through the embedded code in a software debugger, the processor continues to be clocked asynchronously, making it very difficult to exactly reproduce the test if required. This can create an open-loop in debugging if you are not able to identify the failure on your first attempt.
ZeBu Post-Run Debug (zPRD) provides a deterministic framework to implement smart debugging in a closed-loop, cycle-reproducible environment. With zPRD, you can elect to rewind the test to any cycle you select, and apply new debugging tasks, such as waveform dumping, forcing signals, and updating memory contents. zPRD ensures that you never lose a bug once it's been discovered.
ZeBu's Smart Debug Enables fast isolation of problems using system-level tools