The Synopsys ZeBu® Server-3 emulation system builds on the proven ZeBu Server architecture, improving performance by up to 4X and boosting capacity by 3X. This performance level enables system-on-chip (SoC) development teams to speed hardware/software bring-up, OS boot and full-chip verification for faster time-to-market.
With its comprehensive debug capabilities, automated software and tight integration with leading verification and system level tool flows, ZeBu Server-3 delivers a highly productive environment for complex SoC verification. It provides multiple verification use modes, including power-aware emulation, simulation acceleration, in-circuit emulation, synthesizable testbench, transaction-based verification and hybrid emulation for deployment flexibility based on project requirements. Because of its small footprint, low weight, modest power/cooling requirements and high reliability, ZeBu Server-3 offers a lower total cost of ownership. ZeBu Server-3 offers the industry’s largest design capacity, supporting chips as big as three billion gates with a highly scalable architecture based on high-density 28-nanometer (nm) FPGA technology.
- ZeBu Server-3 Highlights:
- High performance emulation system – run days of system level tests in hours
- Comprehensive debug with full signal visibility and Verdi3™ system integration
- Advanced use modes, including power management verification and hybrid emulation with virtual prototypes for architecture optimization and software development
- Advanced architecture for lower total cost of ownership
- Highest capacity – scalable to three billion gates
The performance, capacity, reliability and power-efficiency of an emulator are strongly correlated with the capacity of the chips it uses to represent the design-under-test. Larger emulator chips can generally run the design-under-test at higher speeds, with fewer partitions and lower power-per-gate. Each new generation of ZeBu Server takes advantage of the continued rapid growth in FPGA capacity by adopting the most advanced silicon. ZeBu Server-3 continues this approach by utilizing one of the largest devices currently available – the Xilinx Virtex-7 XC7V2000T with 28 nm Stacked Silicon Interconnect (SSI) technology.
Operating an emulator traditionally implies significant expense beyond the initial system purchase. ZeBu Server-3’s compact and efficient hardware platform is designed to operate in a standard data center environment with power, cooling and weight requirements consistent with other data center equipment. For example, a 300 million gate ZeBu Server-3 configuration requires just a 20-inch cube of space, consumes only 2.5 kW of power and weighs less than 155 pounds – many times lower than required by other emulators with similar capacity. This means that ZeBu Server-3 can usually be installed and used with the existing power and cooling infrastructure in an existing facility rather than requiring expensive construction or space retrofits.
Download the ZeBu Server-3 Datasheet.
- Design capacity: Scalable to 3 billion ASIC gates;
- Multiple users: Up to 49 users in a single configuration
- High performance test environment: High bandwidth, low-latency connectivity to host for streaming transactors, software checkers, assertion output, and waveform generation
- Rapid setup: Completely automated compiler, starting from SoC RTL, requiring no RTL modifications
- zFAST: ZeBu Fast Synthesis for high speed, parallel, incremental synthesis with memory inference and preservation of RTL names
- Memory compiler: Supports an unlimited number of ports, scriptable for easy ASIC library conversion
- Comprehensive debugging: Run-time access to all register & signals without recompilation; interactive combinational signal access(iCSA) leveraging Verdi integration, FSDB waveforms for high speed tracing and software-based checkers; synthesizable SystemVerilog Assertion (SVA) support and reporting for coverage, and the ability to setup a deterministic debug environment that will rewind to any desired point in multi-billion cycle tests and allow you to replicate a test sequence to trace any identified bug.
- Third-party verification and system-level tool integration: co-simulation with commercial HDL simulators and virtual platforms, integration with software development environments