Functional verification is a daunting task. As chip densities grow, so does the complexity of verifying the functional behavior of the design. To compound the problem, the complexity of functional verification grows faster than design density because of the additional interaction between the growing quantities of functional units, 3rd party IP blocks within the design, and embedded and system-level software. Verification at this level of complexity requires billions of cycles of execution. Simulation acceleration, also known as co-emulation, combines functional simulation with emulation hardware, and delivers the performance. Simulation acceleration provides the additional verification performance needed for today’s largest, billion-gate SoCs.
Synopsys' Simulation Acceleration Model
ZeBu co-emulation provides the MHz performance required for large scale SoC debug in a proven simulation environment. All ZeBu emulators are capable of HDL co-emulation, functioning as a simulation accelerator to provide more simulation throughput. Requiring no changes to your existing verification environment, it provides immediate RTL acceleration even for testbenches that rely on the most advanced verification methodologies available today. Furthermore, the use of ZeBu emulators in HW verification can be extended to the transaction-level, enabling even greater performance gains. ZeBu emulators are compatible with advanced verification methodologies such as UMM, VMM and OVM and fully support all popular simulators, including VCS, Cadence Incisive and Mentor Graphics Questa.