Discovery Verification IP  

Next-Generation VIP Architecture 

Discovery™ Verification IP (VIP) is a next-generation VIP written entirely in SystemVerilog and based on the proven VIPER Architecture to deliver greater performance, ease-of-use and extensibility to speed and simplify the verification of the most complex protocols and SoC designs. The Protocol Analyzer available with the Discovery VIP family, is simulator independent enabling users to quickly debug protocols with any verification environment and easily share protocol-based simulation results across teams.

PDFDiscovery Verification IP Datasheet

PDFProtocol Analyzer datasheet

Protocol Analyzer Video vs. Protocol Analyzer Video
Protocol Analyzer Video

100% SystemVerilog, Native UVM, VMM and OVM
Discovery VIP is implemented entirely in SystemVerilog and architected for native support for UVM, VMM and OVM without the need for methodology-level interoperability wrappers or language translations. It provides full visibility into classes, callbacks, and messages and enables true SystemVerilog-based constraints. This streamlining of the VIP structure results in much greater performance and methodology support; it also provides support across all simulators without degrading performance or methodology.

Discovery VIP includes productivity features to accelerate complex tasks like configuration and debug. It also provides features that address the need for protocol expertise and accelerate time to coverage-closure including built-in test-plans, coverage and sequences.

Discovery Verification IP
Figure 1. Synopsys Discovery VIP

Protocol Analyzer
With today’s complex protocols, debug has become one of the most difficult and time-consuming aspects of functional verification. Synopsys’ Protocol Analyzer, available with the Discovery VIP family, provides protocol-centric debug and intelligent visibility. The protocol Analyzer gives users a graphical view of the transfers, transaction, packets and handshaking of a protocol. It highlights relationships across the protocol hierarchy, visually unraveling the complex behavior of highly interleaved traffic. Errors, warnings and messages are annotated to quickly find problems in the simulation. This capability enables engineers to quickly understand protocol activity, identify bottlenecks and debug unexpected behavior.

VIPER Architecture
The Discovery VIP family is based on Synopsys’ new VIPER architecture, which has been engineered from the ground up for enhanced VIP performance, configurability, portability, debug, coverage management, and extensibility. The bulk of VIPER’s functionality and protocol correctness-checking comes from a layered protocol architecture implemented in SystemVerilog using best practices for all methodologies, including UVM, VMM and OVM. All layers are visible, providing complete controllability of protocol verification. Verification engineers are able to work at the highest layer required to meet their verification plans, yet are still able to inject errors at the lowest layers.

Synopsys Verification IP
Synopsys offers VIP for USB 3.0, USB 2.0, HDMI, AMBA AXI3, AXI4, ACE, Ethernet, PCI Express, MIPI (CSI-2, DigRF v4, DSI, HSICSI-2, etc.), SATA, OCP, and several others. See the complete list at

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