With today's complex protocols and memory, debug has become one of the most difficult and time-consuming aspects of functional verification. Verdi Protocol Analyzer, available with the VC Verification IP (VIP) portfolio, is a simulator independent, protocol and memory aware debug environment that enables users to quickly debug with any verification environment and easily share simulation results across teams.
Verdi Protocol Analyzer gives users a graphical view of the transfers, transaction, packets and handshaking of a protocol. It highlights relationships across the hierarchy, visually unraveling the complex behavior of highly interleaved traffic. Verdi Protocol Analyzer enables engineers to quickly understand protocol activity, identify bottlenecks and debug unexpected behavior. Errors, warnings and messages are annotated to rapidly identify problems in the simulation. It is integrated with Synopsys' Verdi and DVE to easily track behavior between protocol views and signal views.
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Complex Protocols Drive Growing Debug Challenge
The growth in complexity and increasing number of protocols used on SoCs is creating a rapidly increasing verification challenge and debug bottleneck for verification engineers. Verification engineers must quickly become protocol experts and try to correlate information across different sources of information to find root cause of problems. Traditional debug methodologies use a combination of loosely connected waveforms, log-files, messages and documentation, which are insufficient for productive debug. Verdi Protocol Analyzer, on the other hand, brings all of the debug information into one place and provides protocol awareness to simplify root-cause analysis.
Figure 1. Verdi Protocol Analyzer Trace Windows showing ARM® AMBA® AXI4™ and USB3