As the number of standard interfaces on SoC designs continues to increase in number and complexity, verification engineers are faced with tremendous challenges to complete both integration and system verification. Synopsys is leading the effort to solve these challenges with Verification IP that simplifies testbench development, provides better coverage and delivers significant improvements in simulation runtime performance.
The VCS Verification Library provides access to a wide portfolio of proven verification IP and allows users to mix and match as many of the verification IPs as needed in a testbench to provide high flexibility and optimal license usage across an organization. The verification IP’s include support for the Verification Methodology Manual (VMM) for SystemVerilog and provide up to 5X improvement in runtime performance when used with VCS. Contact your local Synopsys representative for information on UVM support.
The VCS Verification Library of verification IP's integrate easily into Verilog, SystemVerilog, VHDL and OpenVera testbenches to generate standard bus traffic and error conditions, and check for errors. Monitors provide coverage reports to show functional coverage of the bus protocols.
VCS Verification Library Datasheet