White Papers 

Rethinking SoC Verification
The industry is at an inflection point that calls for new, integrated verification solutions that will offer a fundamental shift forward in productivity, performance, capacity and functionality. Synopsys is meeting this demand with Verification Compiler™. Verification Compiler provides the software capabilities, technology, methodologies and VIP required for the functional verification of advanced SoC designs in one solution.
Rebecca Lipon, Synopsys

Transaction Debug with Verdi
SoC design is complex. It involves both software and hardware design that calls for a higher level of abstraction to ensure accurate verification. Transaction-level verification and debug offers this higher abstraction, while staying close to actual hardware signals. Traditionally, its use has been limited by the lack of a better mechanism and database to capture the critical information needed to do transaction debug, and a better way to view transaction data once captured. Through transaction debug, Verdi now enables users to maintain both the higher level of abstraction of a software debug environment with a direct connection to hardware signal data, thereby correlating their software and hardware debug approaches.
Rich Chang, Synopsys

Enabling Synchronized Hardware Software Debug with Verdi³
Verdi³™ HW SW Debug is an instruction-accurate embedded processor debug solution that offers fully synchronized views between hardware, as RTL or gate-level design models, and software, as C or assembly code — enabling co-debug between RTL and software.
Alex Wakefield, Synopsys; Joerg Richter, Synopsys

Advanced Verification IP Accelerates PCIe Integration Test
PCI Express is an excellent example of where design reuse and adoption has become the norm for design teams, so while the verification teams are no longer faced with full compliance testing they are still challenged with validating that the PCI Express (PCIe) design IP is functioning correctly in the context of the SoC. Clearly, this has a major effect on the verification effort. After all, the verification teams working on integration test shouldn't need to worry about compliance; that should have been taken care of by the IP provider's extensive verification, certification and wide usage in the industry. This whitepaper gives a few pointers on what should be included in integration test and how to get it done efficiently.
Neill Mullinger, Synopsys

Ten Things You Should Know About Verification IP
This fact sheet discusses how to select verification IP (VIP) to maximize your productivity. So, you have chosen to look a little deeper into the benefits of commercial VIP. This is the first step on a path to more productive and complete SoC and IP verification: buying VIP instead of building your own avoids a slew of VIP development, quality and support headaches. Now you need to select a VIP vendor and this can be a critical choice. While you will certainly benefit from using commercial VIP, not all VIP are created equal and some will benefit you much more than others. So, how do you figure out a VIP that maximizes your productivity?
Neill Mullinger, Synopsys

Verifying Cache Coherency Protocols with Verification IP
The use of on-chip cache memory helps design teams optimize multicore designs for both power and performance. Synopsys' SystemVerilog-based VIP suite and Reference Verification Platform provides comprehensive support for AMBA ACE cache coherency, which enables design teams to accelerate the verification of complex multicore SoCs that take advantage of the ACE protocol. The verification suite provides native support for UVM, VMM, and OVM, and includes comprehensive support for generating stimulus sequences as well as automatic built-in checks, coverage and debug capabilities.
Synopsys

The Shifting Landscape of SoC Verification
The next major shift in verification technology will bring about an order-of-magnitude increase in productivity, which will help design teams to address the rising cost of verification.
Michael Sanie, Synopsys

Discovery Verification IP
New Generation of VIP to Address the Growing Challenge of Complex Protocol and SoC Verification.
Neill Mullinger, Synopsys

Solving Modern Verification Challenges
As industry leaders typically are the first to tackle design complexity issues, it is imperative that they deploy a verification solution that they can rely on to meet all of the verification challenges inherent to modern chip design. This white paper outines these verification challenges and the requirements of a verification solution that successfully addresses them.
Michael Sanie, Badri Gopalan

Solving Graphics IC Verification Challenges
Successful, on-time delivery of graphics ICs places tremendous pressure on the required verification process and solution. This whitepaper briefly describes the challenges faced when verifying graphics ICs, the requirements for verification solutions that meet those specific challenges and innovative technologies and capabilities offered by VCS.
Michael Sanie, Badri Gopalan

Solving Networking IC Verification Challenges
Successful, on-time delivery of networking ICs places tremendous pressure on the required verification process and solution. This whitepaper briefly describes the challenges faced when verifying networking ICs, the requirements for verification solutions that meet those specific challenges and innovative technologies and capabilities offered by VCS.
Michael Sanie, Badri Gopalan

Solving Processor IC Verification Challenges
Successful, on-time delivery of processors places tremendous pressure on the required verification process and solution. This whitepaper briefly describes the challenges faced when verifying processors, the requirements for verification solutions that meet those specific challenges and innovative technologies and capabilities offered by VCS.
Michael Sanie, Badri Gopalan

Solving SoC Verification Challenges
Successful, on-time delivery of processors places tremendous pressure on the required verification process and solution. This whitepaper briefly describes the challenges faced when verifying processors, the requirements for verification solutions that meet those specific challenges and innovative technologies and capabilities offered by VCS.
Michael Sanie, Badri Gopalan

VCS Multicore White Paper
This white paper provides a detailed overview of VCS multicore technology, which improves verification performance by taking advantage of advances in the compute infrastructure. VCS multicore technology cuts verification time in half by harnessing the power of modern multicore CPUs and allows designers to identify performance bottlenecks and distribute time-consuming activities across multiple cores for faster functional verification and debug. Automatic partitioning and load balancing, event synchronization and memory optimization make VCS multicore unique for high-performance functional verification. Multicore technology combines the speed-up from parallel computation with the industry-leading Native Testbench (NTB) compiler optimization technique to deliver unmatched verification performance for large-scale designs for chip-level and system-level verification.
Usha Gaira, Sanjay Sawant

VCS: Built for Tough Verification Technology Brief
In this technology brief, you will learn how VCS has built on its track record and has significantly improved functional verification with two more recent industry-first innovations - one, VCS Multicore, in the area of verification speed, and the second, Echo testbench coverage convergence, in the area of verification automation. In addition to these, VCS delivers innovations in construct support and performance leadership for SystemVerilog.
Michael Sanie, Badri Gopalan

Low Power Verification for Multi-rail Cells
Multi-voltage designs have become increasingly common in order to achieve low power. Multiple supply rails are an essential part of multi-voltage designs. Assuming that all output pins in a logic cone are related to a single supply voltage can cause functional failures in silicon or excessive power loss. Consequently, verification tools need to understand the relationship between the driving voltage rails and the impact on each output pin to accurately resolve the logic values. Synopsys’ Eclypse solution provides an infrastructure to capture the necessary information and MVSIM and MVRC are able to use the information to accurately verify multi-rail designs and lead to silicon success. This white paper discusses the challenges faced with static and dynamic verification of multi-rail cells in the context of low power designs.
Prapanna Tiwari, Synopsys, Inc.

Are We There Yet
How do you know when you have run enough random tests? A constraint-driven random environment requires comprehensive coverage data, which often leads to information overload.
Nancy Pratt, Dwight Eddy

A Fully Reusable RegisterMemory Access Solution Using VMM RAL
Register structure and memory modeling is a very complex task of any verification methodology.
Paul Lungu, Bo Zhu

Five Vital Steps to a Robust Testbench with DesignWare Verificatio IP
Verification is one of the biggest challenges for System-on-Chip (SoC) designs, and traditional methods have run out of steam.
Charles Li, Ashesh Doshi

Transaction-level Modeling: SystemC or SystemVerilog?
Today’s chip design requires extensive system-level simulations to ensure that the right architectural trade-offs are made.
Janick Bergeron, Scientist, Synopsys, Inc.

SystemVerilog for e Experts
This document identifies the major differences between the e language as defined by the IEEE P1647/ D6 draft standard and the SystemVerilog language as defined by the IEEE Std. 1800™ 2005 standard.
Janick Bergeron Synopsys Scientist



NewsArticlesBlogsSuccess StoriesWhite PapersWebinarsVideosTraining Courses