|An Approach for Efficient IP Reuse in a Hierarchical UPF Methodology|
This webinar will help you understand a Liberty-based approach for effective IP reuse in implementation of a multi-voltage hierarchical design using the IEEE 1801 (UPF) standard.
Viswanath K. Ramanathan, Corporate Applications Engineer, Synopsys; Mary Ann White, Director of Product Marketing, Synopsys
Feb 26, 2015
|Avoiding the Common Pitfalls of ARM-based Cache-coherent Verification and Performance Analysis|
Synopsys will cover how verification IP for AMBA enables users to generate correct and interesting coherent stimulus for cache coherent SoC verification. This will include the complexities of configuration, stimulus, coverage and checking, as well as how to address the common verification pitfalls.
Neill Mullinger, Product Marketing Manager for Verification IP, Synopsys; Tushar Mattu, Corporate Application Engineer (CAE) for Verification Group, Synopsys
Dec 03, 2014
|The 10 Things to Know About Memory Verification: Synopsys Memory VIP|
Learn how feature-rich, native SystemVerilog memory VIP rapidly verifies the memory interfaces on complex designs, focusing on 10 key areas where productivity is improved.
Neill Mullinger, Product Marketing Manager for Verification IP, Synopsys; Nasib Naser, PhD, Senior Staff Corporate Applications Engineer, Synopsys
Oct 23, 2014
|Reinventing Coverage and Planning with Verdi—A Fully Integrated, Complete Verification Closure Flow To Help You Deliver Chips On Time|
The Synopsys Verdi® Coverage solution provides comprehensive planning and coverage analysis technologies as a part of the industry-leading Verdi3™Automated Debug System. We'll discuss why Synopsys' native integration of planning, coverage, and debug technologies provide a complete closure solution to help meet demanding schedules and provide teams with more confidence when asked the inevitable question: '"Are we done yet?"
Steve Chappell, Senior Product Marketing Manager, Debug and Analysis, Synopsys; Michael Horn, Verification Technologist, Synopsys
Oct 14, 2014
|Addressing IP Compliance Challenges with UVM-based Test Suites|
Protocol verification is a massive time- and resource-consuming endeavor, fraught with complexity and the risk of errors and omissions. Synopsys Verification Test Suites leverage the expertise of protocol experts to provide a rapidly deployable and extensible set of comprehensive tests, written in easily modifiable and reusable SystemVerilog UVM source code. The webinar will give an overview of the architecture and scope of Synopsys’ Verification Test Suites to achieve faster and higher quality coverage closure.
Neill Mullinger, Product Marketing Manager for Verification IP, Synopsys; Karim Aoua, Staff CAE, Synopsys
Sep 30, 2014
|Creating a High-Performance TBE Environment|
Transaction-based emulation or TBE has become an increasingly popular method for utilizing emulators because of the high verification performance and flexibility in connecting to existing environments.
Lance Tamura, CAE Manager, Verification Group, Synopsys
Aug 12, 2014
|Advanced Mixed-Signal Design and Verification of Smartcar ICs|
In this webinar, Micronas and Synopsys discuss the breadth of automotive IC applications, challenges in design implementation and verification and the solutions that stemmed from their collaboration.
Mario Anton, Micronas; Gernot Koch, Micronas; Marco Casale-Rossi, Synopsys
Jul 31, 2014
|Imagination and Synopsys: Reduce Dynamic Power and Area up to 50% on a GHz+ MIPS Core Implementation|
In this webinar, Imagination Technologies will share how their selection of standard cell architecture and use of several dynamic power techniques available in Design Compiler and IC Compiler helped them achieve optimal power and area savings for their MIPS family of CPU cores.
Maya Mohan, Hardware Design Engineer, Imagination Technologies and Jeffrey Lee, CAE Manager, Power Compiler, Synopsys
Jul 10, 2014
|Extending Proven Digital Verification Techniques for Mixed-Signal SoCs with VCS AMS|
VCS AMS provides mixed-signal verification with a unique performance advantage due to tight integration of VCS functional verification and CustomSim FastSPICE simulation. Webinar topics include an introduction of the new VCS AMS mixed-signal verification solution, RNM with VCS, the SystemVerilog-based AMS testbench methodology, low power verification using UPF power intent specification and AMS debug with Verdi.
Rebecca Lipon, Senior Product Marketing Manager, Verification Group, Synopsys; Arturo Salz, Synopsys Scientist, Verification Group, Synopsys
May 21, 2014
|Using a Golden UPF Methodology for Low Power Designs|
This webinar will help you understand the best practices for implementation of a Golden UPF flow for Multi-Voltage designs using the IEEE 1801 (UPF) standard.
Somil Ingle, Sr. Corporate Applications Engineer, Synopsys; Mary Ann White, Product Marketing Director, Synopsys
Apr 03, 2014
|Integrate your Debug Platform Seamlessly with Verdi Interoperable Apps (VIA)|
Learn how Verdi, the industry’s de facto debug platform, offers a fully extensible platform for SoC teams and third-party EDA vendors to develop innovative debug capabilities to address this growing challenge in the industry. The Verdi Interoperability Apps (VIA) opens the programming interface of Verdi letting developers to integrate flow on Verdi Debug Platform.
Rich Chang, Product Marketing Manager, Synopsys; Archie Feng, CAE, Synopsys
Dec 18, 2013
|Effective Verification of ARM AMBA 5 CHI Interconnect-Based SoCs Using Next-Generation VIP|
This webinar will show how Synopsys' next-generation Verification IP enables the rapid creation of a multi-protocol verification environment for an AMBA® 5 CHI interconnect, including CHI, ACE-Lite™ and other AMBA interfaces. The webinar will cover stimulus, system-wide coherency and data integrity checking, performance checking, protocol-aware debug and coverage.
Neill Mullinger, Product Marketing Manager for Verification IP, Synopsys; Tushar Mattu Corporate Application Engineer (CAE) for Verification Group, Synopsys
Nov 20, 2013
|VCS Xprop: Catch X-Related Issues at RTL to Reduce Time-Consuming Gate-Level Simulations|
In this webinar you'll learn about a new technology in VCS, called Xprop, which eliminates 'x' optimism at RTL to enable correlation with hardware design behavior. Xprop can be used to reduce and potentially eliminate gate-level simulations for 'x' validation. This webinar will also show how VCS® Xprop eliminates 'x' optimism in advanced simulation flows (such as VCS-NLP) and demonstrate how to debug 'x'-related issues identified by VCS-NLP and Xprop using Verdi™ Power-Aware Debug.
Rebecca Lipon, Senior Product Marketing Manager, Verification Group, Synopsys
Nov 05, 2013
|How VCS Improves Coverage Driven Verification Efficiency with Integrated Planning and Management|
VCS provides a scalable and integrated planning, management and analysis solution for metric-driven verification. In this webinar, you'll learn how to track coverage and test data in order to correlate results with project goals and resources, so teams know where they are in the verification process and how they have allocated resources. These features are available in VCS 2013.06.
Rebecca Lipon, Senior Product Marketing Manager, Verification Group, Synopsys; Bart Thielges, R&D, Verification Group, Synopsys
Sep 17, 2013
|Improve Stimulus Quality and Verification Completeness with VCS Constraint Debug|
In this webinar, you will learn about new constraint debug features available in VCS 2013.06. In the batch mode, we will show you how to debug solver solutions as well as improve solver performance. In the interactive mode, we will show you how to stop the simulation on randomize calls, explore the solution and relation spaces in the randomize call, examine the solution distribution of random variables, and modify constraints, re-compiling the design interactively for effective what-if analysis.
Rebecca Lipon, Senior Product Marketing Manager, Synopsys; Jason Chen, CAE, Synopsys; Dhiraj Goswami, Scientist, R&D, Synopsys
Jun 25, 2013
|Verilog-to-Verilog Equivalence Checking Using ESP|
This Webinar gives a quick introduction to ESP-CV and how recent features are used to verify various Verilog-to-Verilog scenarios. Coverage analysis of the results is also discussed.
Philip Schmidt, R&D Manager, Synopsys; Dave Hedges, Corporate Applications Engineer, Synopsys
May 29, 2013
|Transaction Debug with Verdi3|
In this webinar, you'll learn how to maximize your productivity by using Verdi's Transaction Debugging technology to dump, visualize and trace transactions. You'll learn how the tool's vertical correlation allows you to take the debug to the signal level waveform while retaining all of the necessary debugging details.
Rich Chang, Product Marketing Manager for Debug, Synopsys
May 22, 2013
|A Hierarchical, Low Power Design Approach for Gigascale Designs|
This webinar will help you understand the best practices for implementation of a Multi-Voltage hierarchical design using the IEEE 1801 (UPF) standard.
Viswanath K. Ramanathan, Corporate Applications Engineer, Synopsys; Mary Ann White, Director of Product Marketing, Synopsys
Apr 24, 2013
|Verifying Advanced Low Power Designs: Find Design-Killing LP Bugs Early and Easily|
Learn how VCS with MVSIM Native Low Power provide the accuracy and comprehensive LP support needed at RTL, and enable LP bugs to be found and fixed early and easily in the design cycle.
David Hsu, Director of Product Marketing, Static and Low Power Verification, Synopsys; Aditya Kher, Senior Corporate Application Engineer (CAE), Low Power Verification, Synopsys; Harsh Chilwal, Senior R&D Engineer, Synopsys
Apr 04, 2013
|Accelerate PCIe Integration Testing with Next-Generation Discovery VIP|
Learn an optimal strategy for integration testing using UVM in conjunction with next-generation features of PCIe VIP for more efficient test development, error injection and debug.
Neill Mullinger, Product Marketing Manager, Synopsys; Paul Graykowski, Corporate Application Engineer (CAE), Synopsys
Mar 20, 2013
|Functional Signoff: Measuring and Improving Verification Quality to Ensure Bug-Free Designs|
In this webinar you will learn how Certitude Functional Qualification can be added to traditional coverage techniques, to provide unique insight into the quality of RTL simulation and formal verification environments. Certitude uses a proprietary mutation-based process to insert “artificial bugs” or faults into the design and measure the ability of your existing verification environment to detect these faults. The results of this process provide an objective measure of overall verification quality – the ability of the environment to activate, propagate and detect potential bugs – and identify specific holes and weaknesses like incomplete test scenarios, missing checkers and assertions, or infrastructure problems that can allow RTL bugs to slip through the process undetected. Fixing these weaknesses makes your verification environment stronger and reduces the risk of signing off or taping out with functional bugs.
Rebecca Lipon, Senior Product Marketing Manager, Verification Group, Synopsys; George Bakewell, CAE Director, Verification Group, Synopsys
Jan 10, 2013
|Using Advanced Verification IP Capabilities to Accelerate Ethernet Verification|
This webinar will be based around a typical Ethernet switch design including a processor, switch fabric and Ethernet MACs. Learn how SystemVerilog, UVM and VIP are utilized to verify the Ethernet digital core and then integration of the core into the system. We also cover advanced VIP features, including test suite and debug, to accelerate productivity.
Neill Mullinger, Product Marketing Manager for Verification IP,
Synopsys; Jaspreet Singh Gambhir, R&D Manager for Verification IP, Synopsys
Dec 11, 2012
|Static Verification of Advanced Low Power Designs|
Learn about advanced low power techniques and the static checking capabilities designers need to verify the consistency and correctness of low power intent and implementation through the flow.
David Hsu, Director of Product Marketing, Static and Low Power Verification, Synopsys; Vinay Srinivas, R&D Group Director, Low Power Verification, Synopsys; Prapanna Tiwari , CAE Manager, Low Power Verification, Synopsys
Oct 30, 2012
|New Features and Methodologies for Simplifying Hierarchical Low Power Verification with Formality|
This webinar will discuss new features in Formality to help make low power hierarchical verification easer. We will also cover how to write your power intent (UPF) to help you implement a robust, simplified, hierarchical verification flow.
Bob Hatt, Corporate Applications Engineer, Synopsys
Oct 10, 2012
|Accurate Early Stage Power Estimation with PrimeTime PX: The NVIDIA Experience|
In this webinar we will review the need for early power analysis, and show how useful power estimates can be achieved even with early and/or incomplete data. NVIDIA will outline their strategies.
Miodrag Vujkovic, Senior ASIC Design Engineer, NVIDIA; Maria Tovey, Corporate Applications Engineer, Synopsys
Oct 04, 2012
|Deploying UVM Effectively: How to Simplify Testbench Debug and Improve Turn-around-time with VCS|
Learn how to utilize VCS and DVE to most effectively deploy, debug and optimize UVM testbenches.
Rebecca Lipon, Senior Product Marketing Manager, Verification Group, Synopsys; Adiel Khan, Corporate Applications Engineer (CAE), Verification Group, Synopsys
Oct 02, 2012
|Verification of MIPI Protocols on a Mobile Platform SoC|
This webinar is based around a MIPI-based mobile platform that consists of an application processor, baseband IC and RF IC with interfaces to the peripheral devices like camera, and display. The Webinar shows how SystemVerilog, UVM and verification IP (VIP) are utilized to verify the SoC that implements that platform. It will specifically focus on how to validate the data flow for typical scenarios involving the camera (CSI) and display (DSI) interfaces.
Neill Mullinger, Product Marketing Manager for Verification IP, Synopsys; Narasimhababu GVL, Senior R&D Manager for Verification IP, Synopsys
Aug 07, 2012
|5X Faster PrimeTime Multivoltage Timing Signoff: A Renesas Case Study|
Learn how PrimeTime’s new multivoltage aware analysis technology reduces risk and speeds signoff for designs with multiple voltage domains, and how Renesas has successfully deployed it to reduce signoff turnaround time by 5X.
Francis Cheung, Senior Staff Engineer, EDA Engineering, Engineering Unit , Renesas Electronics America, Inc.; Carol Scemanenco, Senior Staff Engineer, Implementation R&D Group, Synopsys, Inc.
Jul 31, 2012
|Achieving Rapid Verification Convergence of ARM® AMBA® 4 ACE™ Designs using Discovery™ VIP|
Overview of challenges of verifying a coherent design. Shows how the features and architecture of Synopsys’ new Discovery VIP helps overcome these challenges to simplify verification of ACE design.
Abhijeet Khopkar, R&D Manager, Synopsys; Neill Mullinger, Group Marketing Manager, Synopsys
May 08, 2012
|Low Power Designs Made Easy: Create, Visualize and Debug Your Power Intent|
This webinar will show you the various steps to easily generate, view, refine and debug the power intent of your design, as specified with the IEEE 1801 (UPF) format. You will learn effective techniques to speed up the implementation of your advanced low power designs. This webinar will be valuable for both new and experienced users of power intent. You will also have the opportunity to engage in an interactive Q&A session following the technical presentation.
Sebastian Brugnoli, Corporate Applications Engineer, Synopsys; Mary Ann White, Product Marketing Director, Synopsys
Mar 07, 2012
|Lighter, Easier and More Flexible Approaches for Multi-Voltage Low Power Design Specification|
In this webinar you will learn how various ways of describing power intent with IEEE 1801 (UPF) can help you achieve more efficient low power designs. You will also have the opportunity to engage in an interactive Q&A session following the technical presentation.
Somil Ingle, Corporate Applications Engineer, Synopsys; Mary Ann White, Product Marketing Director, Synopsys
Oct 12, 2011
|Reduce Power Consumption 30% with Advanced Synthesis Techniques|
In this webinar you will learn how new advances in clock gating and voltage threshold (Vt) optimization available in Design Compiler can reduce your dynamic and leakage power by 10-30%. An interactive Q&A session follows the technical presentation.
Mary Ann White, Product Marketing Director, Synopsys; Rishi Chawla, Sr. Application Engineering Manager, Synopsys
Apr 14, 2011