Seminar Overview
This free, one-day technical seminar provides an overview of Synopsys' functional verification solution and how leading design teams use these capabilities and technology to help manage verification complexity. Synopsys' advanced functional verification technology includes high-performance simulation engines, constraint solver engines, native testbench, broad SystemVerilog support (VMM, OVM, UVM), verification planning, coverage analysis and closure, an integrated debug environment, new SystemVerilog Verification IPs and other advanced technologies.
Who Should Attend:
Verification engineers and managers
- This Free Seminar Will Cover:
- Managing Complexity
- Maximizing Throughput
- Leveraging Verification IP and Emerging Technologies
- Consolidating Challenging Flows
Primary Seminar Agenda (agenda may vary in some locations)
| Time | Topic | Details |
| 9:00 a.m. | Registration |
9:30 a.m.
-10:30 a.m. | Managing Complexity | This session will provide an overview of the challenges and trends impacting SoC verification. We will review Synopsys' verification solutions to manage increasing complexity with a complete coverage-driven planning, execution, and methodology for complex SoC verification. |
10:30 a.m.
-12:00 p.m. | Maximizing Throughput | This session is about VCS' new features and recent technology enhancements in SystemVerilog (UVM, VMM, OVM) testbench generation and debug, compile turn-around-time, runtime performance, capacity and diagnostic tools. |
| NOON | LUNCH |
1:00 p.m.
-2:30 p.m. | Leveraging VIP and Emerging Technology | Learn how to leverage Synopsys' new SystemVerilog Verification IP and emerging technologies to better address verification challenges and speed up the verification process. In this session, we will review a reference verification flow with the ARM® AMBA® ACE™ protocol. |
2:30 p.m.
-3:30 p.m. | Consolidating Challenging Flows | Learn about the latest advances in AMS co-simulation, x-propagation and low power verification used by leading semiconductor companies to better address growing overall verification costs and debug challenges. |
3:30 p.m.
– 4:00 p.m. | Conclusion |
Verification Seminar Schedule
| Date | Location | Registration |
| June 27, 2012 | Marlborough, MA | REGISTRATION CLOSED |
| July 13, 2012 | Seoul, Korea | REGISTRATION CLOSED |
| August 14, 2012 | Shanghai, China | REGISTRATION CLOSED |
| August 16, 2012 | Beijing, China | REGISTRATION CLOSED |
| August 21, 2012 | Shenzhen, China | REGISTRATION CLOSED |
| August 23, 2012 | Penang, Malaysia | REGISTRATION CLOSED |
| September 12, 2012 | Manila, Philippines | COMING SOON |
| September 20, 2012 | Reading, U.K. | REGISTER NOW |
| September 25, 2012 | Cambridge, U.K. | REGISTER NOW |
| September 25, 2012 | Allentown, Pennsylvania | REGISTER NOW |
| September 27, 2012 | Boulder, CO | REGISTER NOW |
| October 10, 2012 | Sophia-Antipolis, France | COMING SOON |
| October TBD, 2012 | Tokyo, Japan | COMING SOON |