Pioneer NTB 

SystemVerilog Testbench Automation   

Overview
Discovery™ Pioneer-NTB is a full-featured SystemVerilog testbench automation tool for use with popular VHDL and Verilog simulators. Pioneer-NTB enables engineers to easily adopt advanced verification methodologies using open standards in mixed- simulation environments. Pioneer-NTB is built on the powerful, production-proven technologies of Synopsys’ VCS® comprehensive RTL verification solution and Vera® testbench automation tool, and provides instant access to the extensive VCS and Vera ecosystems. Pioneer-NTB also supports the OpenVera® language, enabling existing Vera verification environments to be easily migrated to Pioneer-NTB for up to 2x faster verification runtime performance.

SystemVerilog Testbench Automation

Standards-Based Verification for VHDL/Verilog Designs
Standards-Based Verification for VHDL/Verilog Designs

Key Benefits
  • Support for SystemVerilog verification features enables the creation of highly effective testbench environments using object-oriented techniques, advanced data types, constrained-random stimulus, functional coverage and assertions
  • Support for Synopsys’ Reference Verification Methodology (RVM) and included building-block libraries accelerate the creation of robust, reusable verification environments following industry-best practices for coverage-driven, constrained- random and assertion-based verification techniques
  • Built-in, complete support for SystemVerilog assertions (SVA), a library of over 50 ready-to-use checkers and a library of assertion IP for many popular interface protocol standards enable fast deployment of an assertion-based design- for-verification (DFV) methodology to speed bug detection and increase design quality
  • Built-in functional and assertion coverage metrics and unified coverage reporting provide a comprehensive view of verification goal attainment
  • Fast, native support for the VCS Verification Library of high-quality verification IP speeds development and execution of advanced verification environments for designs incorporating a wide range of standard interface protocols
  • Extensive support of the OpenVera language enables Vera users to easily migrate existing verification environments to Pioneer-NTB for up to 2x faster performance

Full-Featured Testbench Support
Pioneer-NTB provides built-in support for full-featured, compiled testbenches including object-oriented programming, constrained-random stimulus, advanced data types, functional coverage and assertions. Multiple solver engines simultaneously analyze all user-specified constraints to rapidly generate high-quality random stimulus to verify the design for corner-case behavior. These engines, built on the powerful, production-proven verification technologies of VCS and Vera, rapidly solve complex user constraint sets without generating false constraint conflicts, providing high quality of results and productivity.

Full-Reference Verification Methodology
Pioneer-NTB provides full support for Synopsys’ proven Reference Verification Methodology to help designers quickly adopt industry-best practices for verification. RVM makes the constrained-random stimulus generation, functional coverage, and assertion-based verification techniques used by verification experts available to any SoC or IP development team. It includes a testbench base-class library and defines a layered testbench architecture to speed test development and enable the creation of interoperable components to save time and resources on complex verification projects. RVM is fully compliant with the Verification Methodology Manual for SystemVerilog.

Complete Assertion Technologies
Pioneer-NTB includes complete support for assertions to enable engineers to utilize highly effective design-for-verification techniques to find more bugs faster. Pioneer-NTB speeds the deployment of DFV techniques across design teams by providing an easy-to-use assertion checker library, and a powerful assertion IP library.

The assertion IP library contains a set of advanced checkers and monitors that enable the verification of correct design behavior for standards-based interface protocols. As a contributor to verification quality, the assertion IP library components include built-in coverage metrics. The assertion IP library components include PCI®, PCI-X® 2.0, PCI Express®, AMBA™ 2 AHB and APB, 802.11a-g, AGP, SMIA, USB 2.0, DDR2, OCP 2.0, LPC, and CoreConnect™ standards.

The pre-defined library of over 50 assertion checkers makes it very easy for engineers to adopt and deploy DFV without a steep learning curve. Each checker’s source-code implementation can be viewed and customized for the designers’ specific needs.

Furthermore, the assertions are reusable across multiple tools in the Discovery Verification Platform. For example, checkers can be used as properties that can be proven or disproved by Synopsys’ Magellan™ hybrid RTL formal verification tool.

Finally, efficient coverage engines keep track of the coverage metrics for these assertions during all phases of verification. Combined with the constrained-random stimulus generation and self-checking capabilities of Synopsys’ VCS Verification Library, design teams can now create comprehensive block-level and chip-level verification environments that comply with the Reference Verification Methodology to increase design quality and lower development cost.

Functional Coverage
Pioneer-NTB provides high-performance, built-in functional coverage technology to measure the progress towards verification goals, and to identify coverage holes. Functional coverage is captured using Pioneer-NTB’s support for user-defined coverage bins and groups, with either constrained-random or directed tests. Additionally, Pioneer-NTB’s unified coverage capability makes it easy to capture, aggregate and report coverage information across multiple tests. Coverage technology is natively compiled by the tool to deliver high performance and productivity.

Debug and Visualization Environment
Pioneer-NTB includes an easy-to-use verification debug, visualization and analysis environment. The environment enables easy access to multi-threaded testbench, assertions and other verification data along with an intuitive drag-and-drop or menu-and-icon driven user interface. Tcl scripting support is provided for interaction, batch control and customization.

Intuitive Verification Debug and Analysis
Intuitive Verification Debug and Analysis

Innovative Optimization Techniques
At the heart of Pioneer-NTB is "native code generation" technology, which creates highly efficient executable machine code, with support for all native bug-finding technologies including testbench, assertions, verification IP and coverage. Pioneer-NTB delivers up to a 2X increase in verification performance compared with Vera.

Third-Party Simulator Interoperability
Pioneer-NTB is compatible with third-party Verilog, VHDL and mixed-HDL simulators.

For more information on Pioneer-NTB or other Synopsys verification tools, contact your local Synopsys representative, email verify@synopsys.com, or in North America call 1-800-388-9125.



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