|Oct 27, 2014||SK Hynix Accelerates Memory Development with Productivity-Enhancing Debug Apps on Synopsys Verdi|
VC Apps open APIs automate memory testbench generation and debug. SK Hynix, Inc. has addressed their debug challenges by adopting the Synopsys VC Apps open application programming interfaces (APIs) to directly link their internally developed test generation technology to the industry-leading Synopsys Verdi® debug solution and allow their design and verification teams to customize their debug experience and boost debug productivity.
|Oct 14, 2014||Synopsys Enables Superior Verification Planning and Coverage Analysis with Verdi Coverage|
Verdi Coverage enables users to understand project progress, manage regression data, launch verification jobs, track project trends, generate reports and ultimately optimize resource allocation. This solution addresses the growing challenge of verification closure for complex system-on-chips (SoCs) by introducing advanced technology that allows users to quickly create efficient verification plans, integrate third-party and user-defined metrics, link plans to requirement documents, and intuitively track project and test-level metrics across simulation, static checking, formal verification, VIP and FPGA-based prototyping.
|Sep 23, 2014||Synopsys Unveils Verification Continuum to Enable Next Wave of Industry Innovation in Software Bring-Up for Complex SoCs|
Next-generation verification platform to accelerate time-to-market by months. The Synopsys Verification Continuum platform accelerates industry innovation for earlier software bring-up and shorter time-to-market for advanced SoCs. Verification Continuum is built from Synopsys' market-leading and fastest verification technologies providing virtual prototyping, static and formal verification, simulation, emulation, FPGA-based prototyping and debug in a unified environment with verification IP, planning and coverage technology.
|May 28, 2014||Synopsys Bridges Design and Verification with Next-Generation Static and Formal Technology for Verification Compiler|
Synopsys announces the availability of its VC Formal comprehensive formal verification solution, and VC CDC and VC LP advanced static checking solutions. These solutions address the growing verification challenges of complex SoCs by introducing next-generation verification technology that finds bugs earlier, faster and more accurately, as well as accelerates root-cause analysis.
|Apr 23, 2014||Synopsys Announces Industry's First Complete LPDDR4 IP Solution for High-Performance, Low-Power Mobile SoC Designs|
PHY, Controller and Verification IP Deliver up to 3200 Mbps Speeds for High-End Smartphones and Tablets
|Mar 25, 2014||Synopsys Unveils Advanced Mixed-Signal Verification Initiative to Accelerate Regression Testing of Mixed-Signal SoCs|
Initial Components of Initiative Extend Proven Verification Methodology and Technologies for Mixed-Signal Applications
|Mar 04, 2014||Synopsys Introduces Verification Compiler to Enable 3X Productivity|
Synopsys Introduces Verification Compiler to enable 3X productivity and deliver next-generation software technologies for complete verification flow. Verification Compiler is a complete portfolio of integrated, next-generation verification technologies that include advanced debug, static and formal verification, simulation, verification IP and coverage closure to create a complete functional verification flow with a single product.
|Feb 25, 2014||Synopsys Delivers Industry’s Fastest Emulation System|
ZeBu Server-3 speeds hardware-software bring-up, OS boot and SoC verification by up to 4X for faster time-to-market on even the largest designs
|Feb 25, 2014||Imagination Technologies and Synopsys Collaborate to Enable Faster Emulation|
ZeBu Server-3 emulator achieves 3.5 MHz performance on PowerVR Series 6 GPU to speed driver development and SoC verification
|Mar 19, 2013||Micronas Standardizes on Synopsys’ Design and Verification Solutions for Automotive Designs|
Solutions Include Galaxy Custom and Digital Implementation, Discovery Verification Platform
|Jan 30, 2013||Imagination Technologies Selects Synopsys as Advanced Verification Technology Partner|
Multi-year Collaboration Results in Deployment of Synopsys' Advanced Formal Debug Technology for Verification of PowerVR Graphics Intellectual Property (IP) Cores
|Jan 21, 2013||Freescale Boosts Verification Productivity with Synopsys Verification IP|
Companies extend system-on-chip (SoC) verification collaboration on simulation, debug and verification IP. Synopsys today announced advancements in its longstanding verification collaboration with Freescale® Semiconductor. With a focus on addressing the increasing complexities of SoC verification, Freescale teams are leveraging Synopsys' innovations in next-generation verification IP (VIP), simulation performance, debug technology and methodology development. This collaboration is targeted to achieve better schedule predictability and lower overall verification costs for Freescale's complex SoCs.
|Dec 17, 2012||Elliptic Technologies Selects Synopsys' Discovery VIP for ARM AMBA Interconnect for Verification of its Leading Security Systems|
Next-generation Discovery VIP provides high performance, advanced features, and ease-of-use to accelerate SoC verification. Synopsys announced that Elliptic Technologies, a technology leader in embedded security solutions for mobile, networking, smart grid and automotive markets, successfully deployed Synopsys' Discovery Verification IP (VIP) for the ARM® AMBA® protocol for verification of its new-generation Multi-Packet Manager security protocol accelerator (CLP-630). Elliptic cited performance, efficient ease-of-use and smooth deployment as some of the key benefits of Discovery VIP.
|Oct 29, 2012||Synopsys Extends Support for ARM AMBA Protocol Verification with New Performance Checker for AMBA 4 AXI4|
Next-generation Discovery Verification IP Enables Identification and Debug of SoC Performance Bottlenecks. Synopsys announced that its next-generation Discovery™ Verification IP (VIP) for the ARM® AMBA® 4 AXI4™ protocol now offers a Performance Checker capability. This capability enables system-on-chip (SoC) verification teams to analyze and validate SoC performance using metrics established during the system architecture definition process, speeding up the debug of SoC performance bottlenecks.
|Sep 19, 2012||Hitachi Selects Synopsys' Discovery Verification IP for ARM AMBA Interconnect for Verification of its Storage Systems|
Performance, intelligent debug and advanced coverage features led to selection of next-generation VIP. Synopsys today announced that the storage solutions division of Hitachi, Ltd. has selected Synopsys' Discovery™ Verification IP (VIP) for the ARM® AMBA® AXI3™ protocol for verification of Hitachi Virtual Storage Platform. Enabled by Synopsys' next-generation VIPER architecture, Discovery VIP demonstrated a performance advantage over other VIP, as well as delivered protocol-aware debug capabilities and advanced built-in coverage features, which have accelerated Hitachi's Storage Systems verification closure process.
|Aug 08, 2012||Synopsys Launches Industry's First Technical Community Site Dedicated to Users of Verification IP|
The site provides a centralized online resource of relevant forums and blogs focused on verification of industry-standard protocols. VIP-Central.org is the go-to source for the latest technical information and discussions on the use of verification IP and advanced verification methodologies to verify protocol-based IP as well as IP integration, SoC sub-systems and full SoCs. VIP-Central.org aggregates information from industry experts across the verification community, providing best practices and ideas for better verification performance, protocol debug, methodology, verification planning, coverage management and ease-of-use.
|May 14, 2012||AMD Selects Synopsys as a Verification IP Partner|
Expands Collaboration to Further Accelerate SoC Verification. Synopsys, today announced a multi-year agreement to provide Advanced Micro Devices, Inc. (AMD) with its next-generation Discovery™ Verification IP (VIP). Based on the new VIPER architecture, the recently announced Discovery VIP family provides inherent performance, ease-of-use and extensibility to speed and simplify verification of the most complex system-on-chip (SoC) designs. This agreement covers a variety of VIP titles including USB 3.0, ARM® AMBA® AXI™ interconnect, SATA 3.0, PCI Express® Gen 3, and MIPI, as well as Synopsys' Protocol Analyzer, a unique protocol-aware SoC debug environment.
|Mar 22, 2012||Synopsys Extends Leadership in Storage Standards Verification IP with NVM Express|
Offers First-to-Market VIP for the Emerging NVMe Storage Interface Protocol
|Feb 27, 2012||Synopsys Unveils Next-Generation Verification IP for Faster SoC Verification|
Discovery VIP delivers up to 4X faster performance, rapid configurability, efficient protocol-aware debug, and quicker protocol compliance closure
|Feb 27, 2012||SpringSoft and Synopsys Link Debug Technologies to Speed Protocol Verification for SoC Designs|
|Jan 23, 2012||Synopsys Acquires ExpertIO|
|Sep 02, 2011||Synopsys Acquires nSys Design Systems|
|Feb 03, 2011||Synopsys Invites Cadence Incisive and Mentor Graphics Questa Users to the Verification FastForward Program|
VCS support for OVM 2.1.1 and the upcoming UVM 1.0 enables smooth migration to faster verification
|Jul 01, 2009||Synopsys MVSIM Adopted for Low Power Verification of STw8500 Mobile SoC Platform|
Comprehensive Support for Low Power Techniques and High Level of Accuracy Significantly Improve Bug Detection. Synopsys, Inc. today announced that ST-Ericsson has adopted Synopsys' MVSIM low power dynamic verification solution for its STw8500 system-on-chip (SoC) platform for the mobile phone market. ST-Ericsson selected MVSIM for its proven ability to comprehensively verify low power techniques, including standby and built-in automated low power assertions, which enable the early detection of bugs.