AMS Design and Verification Seminars 

Accelerating AMS Design and Verification 

Seminar Overview
These seminars provide a forum for members of the electronic design community to learn about Synopsys' latest technologies and methodologies. These FREE technical seminars will focus on the latest developments in our AMS/custom solutions and learn how to utilize these new capabilities effectively to increase AMS simulation throughput and achieve a higher level of mixed-signal verification and custom implementation productivity. We will cover advancements in SPICE and FastSPICE circuit simulation, mixed-signal verification, AMS debug and analysis, characterization and custom layout implementation

Who Should Attend:
Circuit designers and managers who want to learn how Synopsys can improve custom circuit design and verification productivity.

Primary Seminar Agenda (agenda will vary in some locations)

TimeTopicDetails
9:00 a.m.Welcome
9:10 a.m.AMS OverviewHear how Synopsys is delivering SPICE and FastSPICE performance with every release and how we have integrated best-in-class circuit simulation tools in the Galaxy Implementation and Discovery Verification Platforms to deliver higher verification performance for AMS designs. You will also learn about the advanced and open custom implementation solution based on the Laker custom solution, and how Synopsys is integrating Laker into the Galaxy Implementation Platform to streamline custom design and enable higher productivity.
9:50 a.m.AMS Simulation, Debug and Library CharacterizationLearn how the latest technology advances in HSPICE, FineSim and CustomSim address a wide range of simulation challenges, including FinFET, signal integrity, low-power analysis, reliability and mixed-signal verification. Learn how CustomExplorer Ultra provides a versatile and scalable netlist-based environment for managing thousands of SPICE, FastSPICE or mixed-signal simulations and allows users to find design errors early using its superior analysis and debug capabilities. We will also provide an overview of the SiliconSmart library characterization solution. Learn how SiliconSmart-generated libraries provide exceptional correlation between Synopsys’ PrimeTime signoff and HSPICE simulation tools to meet the stringent timing accuracy requirements for advanced technology nodes.
11:00 a.m. BREAK
11:15 a.m.AMS Simulation, Debug and Library CharacterizationContinuation of morning session
NoonLUNCH
1:00 p.m. Laker Custom Design Environment An overview of the Laker custom design environment—the fast, widely-used interoperable solution for custom design. We will highlight the unique automation features in Laker that deliver big gains in layout productivity, and will also cover the latest enhancements to Laker which add integration to leading Synopsys tools, such as StarRC and IC Validator, to form a complete front-to-back design flow.
1:30 p.m. Laker Advanced-Node Layout We will review how Laker has been updated to support the key custom design challenges posed by 20-nm and below process nodes. Issues such as double-patterning support, the impact of layout-dependent effects, requirements for handling MEOL rules, and implications of FinFET devices will all be covered.
2:00 p.m. BREAK
2:15 p.m. Analog Prototyping with Laker Get a deeper look at Laker's powerful new analog prototyping functionality that provides quick placement of circuits at the device level so designers can get early feedback of layout effects and reduce design iterations. Built on the foundation of Laker's schematic-driven layout, the new analog prototyping technologies advance the state-of-the-art in analog design methodology and dramatically shorten design time.
2:45 p.m. Laker SDL and Analog Prototyping Demonstration See a demonstration of the efficient layout methodology made possible by Laker. The demo will start with an overview of Laker's schematic-driven layout. Key Laker features, such as the stick diagram compiler and matched-device creator, will be highlighted. We will show Laker's full support for 20-nm design rules, such as double-patterning, and then show how Laker's analog prototyping solution builds on the schematic-driven-layout flow to provide an even higher level of custom layout productivity.
3:15 p.m.Conclusion and Prize Draw

AMS Seminar Schedule

DateLocationRegistration
June 18, 2013Shanghai, ChinaCLOSED
June 20, 2013 Beijing, China CLOSED
June 28, 2013 Shenzhen, China (1/2-day) CLOSED
June 27, 2013 Hsinchu, Taiwan CLOSED
June 26, 2013 WuXi, China (1/2-day) CLOSED
July 2, 2013 Reading, UK REGISTRATION OPEN
July 9, 2013 Seoul, Korea REGISTRATION OPEN
July 16, 2013 Cork, IrelandREGISTRATION OPEN
July 17, 2013 Ho Chi Minh City, VietnamREGISTRATION OPEN
July 19, 2013 Hanoi, VietnamREGISTRATION OPEN



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