Videos 


DAC 2013: Advance Your Mixed-Signal Verification Techniques to the Next Level

On June 3, 2013, Synopsys hosted an AMS Luncheon at DAC. At this event, attendees heard what industry leaders from ARM, Broadcom, Micron, ST-Ericsson and STMicroelectronics had to say about using Synopsys’ AMS verification solution in some of today’s most challenging designs.
Farhad Hayat, AMS Marketing Director, Synopsys; George Lattimore, Director of Engineering, ARM; Jaynie Shorb, Principal Design Engineer, Broadcom; Fuad Badrieh, Principal Engineer, Micron; Florian Cacho, AMS Verification Engineer, ST-Ericsson; Sebastien Cliquennois, Sr. Staff Engineer, STMicroelectronics



DAC 2012: Boost Productivity Using Synopsys’ AMS Verification Solution

On June 4, 2012, Synopsys hosted an AMS Luncheon at DAC. At this event, attendees heard what industry leaders from AMD, GLOBALFOUNDRIES, and NVIDIA had to say about using Synopsys’ AMS verification solution in some of today’s most challenging designs.
Scott Wedge, Sr. Staff Engineer, Synopsys; Chad Lackey, MTS Design Engineer, AMD; Zhi-Yuan (Joanne) Wu, Sr. MTS, GLOBALFOUNDRIES; Sunil Sudhakaran, Manager of Hardware Engineering (Signal Integrity), NVIDIA


2012 HSPICE SIG Event: Tackling Design Integrity of Multi-Gbps Systems
2012 HSPICE SIG Event: Tackling Design Integrity of Multi-Gbps Systems

On January 31, 2012, Synopsys hosted an HSPICE SIG Event in Santa Clara, CA. At this event, industry leaders spoke about their experiences using HSPICE in some of their most challenging designs.
Tony Todesco, SMTS Design Engineer, AMD; Johann Nittman, Signal Integrity Engineer, Cavium Networks; Liping Li, Sr. Member of the Technical Staff, Altera; Randy Wolff, Manager, Signal Integrity R&D Group, Micron; Scott Wedge, Sr. Staff Engineer, Synopsys



DAC 2011: SPICE Up Your Chip: Achieving Fast, Accurate AMS Verification

On June 7, 2011, Synopsys hosted an dinner event at DAC in San Diego, CA. Hear what industry leaders from AMD, Juniper Networks, nVidia, Qualcomm and Xilinx had to say about using HSPICE and CustomSim in some of today’s most challenging designs.
Dirk Robinson, Analog Design Engineer, AMD; Nikhil Jayakumar, Design Engineer, Global Circuits Team, Juniper Networks; Wen-Hung Lo, Senior Mixed-Signal Design Engineer, NVIDIA; Mohamed Abu-Rahma, Staff Engineer, Memory Circuit Design Team, Qualcomm; Min-Fang Ho, CAD Manager, IC CAD, Xilinx


Custom Explorer
CustomExplorer Ultra: Mixed-signal Regression Management and Debug Environment

CustomExplorer Ultra is a comprehensive regression management and debug environment for mixed-signal SoC verification. Tightly integrated with Synopsys’ CustomSim simulator and CustomSim/VCS co-simulation solution, CustomExplorer Ultra aids engineers in rapidly performing customized advanced analyses for transistor-level analog, mixed-signal and SoC designs.
Synopsys


HSPICE SIG Video
HSPICE SIG: A Converging Analog World: Silicon, Package and System

On January 31, 2011, Synopsys hosted its first HSPICE SIG Event in Santa Clara, CA. At this event, industry leaders spoke about using HSPICE in some of today's most challenging designs.
Synopsys, Inc.


DAC 2010
DAC 2010: Coping with Modern AMS Verification Challenges

The guest panel of industry experts discussed how they are addressing key verification challenges at 32 nanometers, achieving high-accuracy verification for complex BCD and FPGA applications, and using power management techniques for custom DSP designs.
Satinderjit Singh, Engineering Manager, PIPD, ARM, Ltd.; Yuval Shay, Mixed-Signal Verification Engineer, STMicroelectronics; Mei-Cheng Huang, Mixed-Signal Verification Engineer, AMD; Pierluigi Daglio, AMS Design & Verification Flows Manager, STMicroelectronics; Warren Wong, Vice President, Engineering, Synopsys



DAC 2009: Coping with Modern AMS Challenges

The guest panel of industry experts discussed how they are addressing key verification challenges at 32 nanometers, achieving high-accuracy verification for complex BCD and FPGA applications, and using power management techniques for custom DSP designs.
John Chilton, Sr. VP of Marketing & Corporate Development, Synopsys; Aaron Barker, Staff Engineer, Sun Microsystems; Eugene Chen, CAD Director, Alter; Sandeep Tare, Verification Methodology Engineer, Texas Instruments; Lyes Djama, Smart Power Design Flows Manager; Pierluigi Daglio, AMS Design & Verification Flows Manager, STMicroelectronics



DAC 2009: Solutions for Tough Verification Challenges

Synopsys hosted a special VCS Verification Luncheon event at DAC in San Francisco, CA focused on the VCS functional verification solution. Verification R&D experts from leading companies discussed how they leverage VCS’s multicore performance, transaction-based verification, tight mixed-signal integration, comprehensive low power verification capabilities and proven methodologies to solve today’s toughest verification challenges.
John Chilton, Sr. VP of Marketing & Corporate Development, Synopsys; YC Wong, Director of IC Engineering, Broadcom; Shrenik Mehta, Sr. Director of Frontend Tools and OpenSPARC, Sun Microsystems; Faisal Haque, Director of Engineering, Qualcomm; and Amit Chowdhry, Member of Technical Staff, AMD




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