|FinFET Technology – Understanding and Productizing a New Transistor From TSMC and Synopsys|
This white paper discusses the major challenges with FinFETs and how TSMC has been collaborating with
Synopsys, one of their ecosystem partners, to deliver a complete solution. Key elements of this solution include
comprehensive FinFET profiling without impact to design tool runtime and proven, verified IP availability. The
TSMC 16-nm FinFET solution will ensure mutual customers swiftly move to building the next generation SoCs.
Jason S.T. Chen, TSMC; Andy Biddle, Synopsys
|Custom and Mixed-Signal Design Solution|
Synopsys’ unified solution for custom and cell-based design and verification provides a comprehensive, highly integrated suite of tools for advanced-node mixed-signal SoC design. The high degree of integration and interoperability shortens time-to-tapeout and improves design quality.
|MOS Device Aging Analysis with HSPICE and CustomSim|
MOS Reliability Analysis (MOSRA) in HSPICE and CustomSim offers a robust and economic alternative
to empirical overdesign and extensive lifetime testing.
Bogdan Tudor, Joddy Wang, Weidong Liu, Hany Elhak, Synopsys
|De-risking Variation-aware Custom IC Design with Solido Variation Designer and Synopsys HSPICE|
Challenges in a traditional custom IC variation-aware design flow lead to schedule, product yield, and product quality risks. Solido Variation Designer and Synopsys HSPICE together enable fast and accurate variation-aware design methods that can reduce or remove risks associated with traditional variation-aware design. Together, these tools and methods help to reliably deliver products on schedule that are competitive and cost-effective.
Jeff Dyck, Director of Product Development, Solido Design Automation, Inc.; Kishore Singhal, Scientist, Synopsys
|Accelerating Analog Simulation with HSPICE Precision Parallel Technology|
HSPICE Precision Parallel technology is a new multicore transient simulation extension to HSPICE for both pre- and post-layout of complex analog circuits such as PLLs, ADCs, DACs, SERDES, and other full mixed-signal circuits. HPP addresses the traditional bottleneck in accelerating SPICE on multicore CPUs with new algorithms that enable a larger percentage of the simulation to be parallelized, with no compromise in golden HSPICE accuracy. Additionally, efficient memory management allows simulation of
post-layout circuits larger than 10 million elements.
Robert Daniels, Sr. Staff Engineer, Synopsys Inc.; Harald Von Sosen, Principal Engineer, Synopsys Inc.; Hany Elhak, Product Marketing Manager, Synopsys Inc.
|PLL Noise Analysis with HSPICE RF|
This white paper describes a procedure for efficiently extracting key noise
measurements for a phase locked loop using HSPICE RF. The procedure has been updated to take advantage of several new and unique capabilities in HSPICE RF that can be used to accurately predict PLL
steady-state and phase noise characteristics.
<div>Scott W. Wedge, Ph.D.<br>Synopsys, Inc.</div>
|HSPICE Testbench Technologies for Analog & RFIC Design |
Analog and RF circuits must be designed to meet a diverse set of specifications spanning a broad range
of time-domain and frequency-domain performance goals.
<div>Scott Wedge, Ph.D. Sr. Staff Engineer<br>Synopsys, Inc.</div>