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Analog Insights
Technical content and latest trends about AMS, from Analog to Mixed-signal and RF
Hélène Thibiéroz
A View from the Top: A System-Level Blog
Shift towards adoption of virtual platforms and ESL technologies.
Achim Nohl
On Verification: Software-to-Silicon
Exploring software-to-silicon verification.
Tom Borgstrom
The Standards Game
Observation, information and experiences with technical standards.
Karen Bartleson
Verification Martial Arts
Technical information and tutorials focusing on functional verification.
Janick Bergeron
All Synopsys Blogs
DAC AMS Lunch
Advance Your Mixed-Signal Verification Techniques to the Next Level
HSPICE SIG VIDEOLOG
Leading-edge Modeling for Chip, Package and 3D-IC
HSPICE SI WEBINAR
Open Your Eye with HSPICE Fast & Accurate Eye Diagram Analysis
HSPICE MINI DEMOS
See how HPP technology and StatEye analysis can speed up simulation of analog circuits!
HSPICE TIPS WEBINAR
Reduce simulation time without compromising HSPICE gold-standard accuracy
News
Micronas Standardizes on Synopsys' Design and Verification Solutions for....
Synopsys Accelerates Adoption of FinFET Technology with Production-Proven....
Synopsys to Acquire SpringSoft
Synopsys Acquires Ciranova
Synopsys Mixed-Signal IC Design Solution Qualified for TowerJazz Power....
BiTMICRO Selects Synopsys for Chip Design Automation
Synopsys Completes Acquisition of Magma Design Automation
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All Synopsys News
Articles
The New Mixed-Signal Flow
How VHDL designers can exploit SystemVerilog
Synopsys tries to organize its efforts in EDA multiprocessing
Verify SoCs Faster And More Predictably With SystemVerilog And Constrained-Random Stimuli
VMM application packages- the next level of productivity
IC verification key: ‘Do it step by step, don’t cut corners’
Nightmares in Functional Verification
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Blogs
Analog Insights
A View from the Top: A System-Level Blog
On Verification: Software-to-Silicon
The Standards Game
Verification Martial Arts
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Success Stories
Etron Achieves First-Silicon Success of USB3.0 SoC Using Synopsys Proven Solutions
HSPICE-Quotes
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White Papers
FinFET Technology – Understanding and Productizing a New Transistor From TSMC and Synopsys
Custom and Mixed-Signal Design Solution
MOS Device Aging Analysis with HSPICE and CustomSim
De-risking Variation-aware Custom IC Design with Solido Variation Designer and Synopsys HSPICE
Accelerating Analog Simulation with HSPICE Precision Parallel Technology
PLL Noise Analysis with HSPICE RF
HSPICE Testbench Technologies for Analog & RFIC Design
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Webinars
Discovery-AMS for Mixed-Signal Verification
Open Your Eye with HSPICE
Fast and Accurate Library Characterization
High-Productivity Analog Verification and Debug
Get the Most from Your HSPICE Simulation
Avoid EM & IR-drop Effects in Custom IP Blocks
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Videos
2013 HSPICE SIG Event: Leading-edge Modeling for Chip, Package and 3D-IC
2012 HSPICE SIG Event: Tackling Design Integrity of Multi-Gbps Systems
Introducing HSPICE Precision Parallel Technology
DAC 2011: SPICE Up Your Chip: Achieving Fast, Accurate AMS Verification
HSPICE SIG: A Converging Analog World: Silicon, Package and System
HSPICE Mini Demos
IMS MicroApp Video: Causality Considerations for Multi-Gigabit StatEye Analysis
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NanoSim
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