|Migrating Complex Networking ASIC Verification Environment|
As the computer hardware industry strives to obey Moore’s Law, the telecommunication industry is following the even more rapid phenomena as described by Metcalfe’s Law: the potential number of contacts between each end computer increases rapidly, the effort to reduce the congestion at the network layer is greatly contributing to today’s system-on-chip (SoC) complexity.
Mar 18, 2008
|How VHDL designers can exploit SystemVerilog|
SystemVerilog, the standard that originated from Accellera and is now IEEE1800, is not just for Verilog users. VHDL users can also improve their design processes using its proven verification features.
Mar 15, 2008
|Synopsys tries to organize its efforts in EDA multiprocessing|
It’s hard to imagine a set of applications that need computing resources more than the chain of EDA tools for a 65 nm chip design.
Mar 10, 2008
|Verify SoCs Faster And More Predictably With SystemVerilog And Constrained-Random Stimuli|
Verifying the integration and operation of new IP in a legacy system-on-a-chip (SoC) becomes challenging. This is true particularly when the legacy SoC environment was built using a directed test methodology and validation of new IP requires corner case stimulus to achieve required functional coverage.
Mar 05, 2008
|VMM application packages- the next level of productivity|
The history of the EDA industry shows a clear, repetitive pattern. Designers develop new proprietary technologies, leveraging de facto and sanctioned industry standards; leading-edge users identify the most effective of these new technologies; and the industry turns the knowledge that users gain into the next set of de facto or sanctioned standards, allowing the creation of a set of newer technologies.
Feb 21, 2008
|IC verification key: ‘Do it step by step, don’t cut corners’|
The EDA industry hasn’t come up with a silver bullet to reduce the amount of functional verification IC engineers need to perform to get chips out the door in a timely manner, but adherence to a strict methodology can better your chances of producing chips that avoid respins.
Feb 08, 2008
|Future Verification Appears Uncertain|
A funny thing happened on the way to 45 nm. Verification- once the sleepy backwater arena of the EDA industry- suddenly became massively important. "Verification effort increases exponentially when design size increases linearly," explains Tom Borgstrom, Director of Solutions Marketing at Synopsys.
Oct 15, 2007
|Power-Sensitive 65nm Designs Increase the Need for Transistor-Level Verification|
The vision expressed in Moore's Law; that the number of transistors on a chip would double approximately every two years, has been driving the semiconductor industry for many process generations.
Aug 27, 2007
|Synopsys, Zuken tie simulation to boards|
Promising an integrated platform for system-level electronic design, simulation, and verification, Synopsys Inc. and Zuken have announced a partnership to link Synopsys' Saber mixed-signal simulator to Zuken's CR-5000 pc-board design environment.
May 30, 2007
|Start at the Top to Reduce Re-Spins for Analog-Digital Chips|
Modern integrated-circuit design methodologies and advanced process technologies can produce complex mixed-signal devices. These devices, which are known as systems-on-a-chip (SoCs), feature a large number of digital, analog, and RF cores on a single chip.
Jun 14, 2005
|What's needed for mixed-signal verification|
eeDesign is the comprehensive source of information for electronics design tools and methodologies. Its scope includes EDA tools, silicon intellectual property (IP), chip design methodologies, and chip and system architectures.
May 28, 2004