This is the IEDM 2013 edition of the TCAD News. In this issue, we provide an overview of Sentaurus I-2013.12 with new features and models to support the development of the latest technologies for logic, memory, analog, power and optoelectronics applications.
In this edition we present the new features and enhancements in the H-2013.03 release of TCAD Sentaurus, which includes a number of important new and updated features addressing the modeling challenges of 10nm FinFET, 3D memory and Si and wide bandgap power devices.
This is the IEDM 2012 edition of the TCAD News. This year marks a new chapter of CMOS innovation with the production release of 22nm FinFET technology to the market, and the semiconductor industry representatives gathering at IEDM will have much to be excited about advancing the FinFET technology below 10nm. Memory technologies are also evolving rapidly, with 3D NAND providing a near term pathway for extending the scaling of Flash technology, and new architectures such as spintransfer torque and resistive RAM undergoing intensive research and development.
This issue focuses mainly on the Sentaurus G-2012.06 Release.
In this special 2011 IEDM edition of TCAD News, we present two articles which are highly relevant to advanced logic and memory technologies. The first article discusses a recently developed Impedance Field Methodology (IFM) for analyzing the impact of random variability on device performance. The second article covers the 3-D simulation of FinFET devices, including the analysis of doping and stress proximity effects.
This edition of TCAD News is dedicated to the F-2011.09 release of TCAD Sentaurus which supports the latest processes (plasma implantation, silicon stress and orientation-dependent mobility), modeling 3D structures (shapes library, crystallographic etch and deposition, line-edge roughness, Sentaurus Topography 3D interface), and simulating device variability with the Impedance Field Method.
This edition reports on the use of TCAD Sentaurus for modeling two wide-bandgap power devices. The first article discusses the simulation of a normally off p-gate GaN HEMT, and the second article discusses the simulation of a SiC IGBT in Sentaurus Device.
This issue has two articles; the first discusses the latest TCAD models for simulating negative bias temperature instability, which impacts PMOS device reliability. The second article reviews the effect of hot carriers in semiconductor device operation and reliability, and illustrates the combination of hot-carrier energy and degradation models in simulating channel-initiated secondary-electron (CHISEL) current in flash memory cells.
This newsletter highlights the new features and enhancements in TCAD Sentaurus Version E-2010.12. In addition, there is an introduction to Sentaurus Interconnect, the latest addition to the TCAD Sentaurus product family, as well as two other articles, one describing a three-dimensional simulation flow of a six-transistor SRAM cell and one addressing variability in FinFET devices.
This edition presents a case study for a high-efficiency silicon solar-cell whose structure requires 3D simulation. The second article describes a 32-nm CMOS simulation flow, which showcases the latest Sentaurus capabilities for modeling stress engineering and high-k/metal gate processes.
This issue has a special focus on power device technologies in view of the 2010 International Symposium on Power Semiconductor Devices and ICs (ISPSD). Simulations focus on silicon-based devices and on the new areas opened up by silicon carbide (SiC) and gallium nitride (GaN). In addition, there is a concise article on a new oxidation feature in Sentaurus Process Kinetic Monte Carlo.
This edition is dedicated to the new features, capabilities and enhancements in TCAD Sentaurus Version D-2010.03. Three-dimensional simulation and new models for advanced technologies are well represented in both process and device simulation.
This issue focuses on two topics of concern for current and future development of CMOS devices: the simulation of random dopant fluctuation effects in TCAD Sentaurus and the application of kinetic Monte Carlo simulation to ultrashallow junction formation.
This edition presents two articles. The first article examines the manufacturing, reliability, and performance analysis of 3D integration structures using through-silicon vias (TSVs), with the simulations performed using Fammos TX. The second article presents the simulation of GaAs-based heterojunction bipolar transistors (HBTs) and pseudomorphic high electron mobility transistors (PHEMTs).
This issue highlights the new features and enhancements in Version C-2009.06 of TCAD Sentaurus. There is special emphasis on the developments in three-dimensional process and device simulations using Sentaurus Process and Sentaurus Device. The second article introduces the band-structure calculator available in Sentaurus Device Monte Carlo in the context of the fundamentals of strain engineering.
This issue focuses on two main areas. The first article reviews the progress achieved in the simulation of multi-junction solar cells, which hold the world record in efficiency and are being used in industrial concentrator photovoltaic installations. The second article highlights the characterization and design of radiation-hardened electronics by looking at recent advances in 3D simulations of SRAM cells.
This newsletter presents 3D simulations of 45-nm CMOS technology devices, the simulation of phase-change memory using Sentaurus Device, performance and reliability trade-offs in metal filling pattern design using Fammos TX and Raphael™, and increased robustness of SiC device simulations with numeric enhancements and material parameter calibration.
This issue highlights the developments and enhancements in Version A-2008.09 of TCAD Sentaurus, TSUPREM-4™, and Medici.
The lead article presents the objectives and technical approach of the European ATOMICS (Advanced Front-End Technology Modeling for Ultimate Integrated Circuits) project, of which Synopsys Switzerland LLC is a partner. In addition, advancements in the integration of Sentaurus Process and Sentaurus Structure Editor are described.
This issue highlights the release of Sentaurus Lithography, the advanced lithography process simulator, which replaced the SOLID product family. Hardware acceleration of electromagnetic simulations for CIS design using Acceleware products is presented, as well as visual optimization and exploration using Sentaurus Workbench Advanced, and 45-nm circuit design using process-aware compact models.
This issue highlights the new features and enhancements in Version A-2007.12 of TCAD Sentaurus, TSUPREM-4™, and Medici. There is also a special article by Dr. Francis Benistant of Chartered Semiconductor that discusses the organization and role of TCAD teams in a modern semiconductor foundry.
This edition presents the simulation of 45-nm CMOS technology in TCAD Sentaurus and multilevel modeling of layout impact on mobility enhancements with dual stress liners using Fammos TX.
The newsletter presents articles on TCAD for electrostatic discharge, TCAD distortion analysis based on the harmonic balance method available in Sentaurus Device, setting up an efficient simulation environment for modeling single event effects with the TCAD Sentaurus tool suite, the impact of gettering effects in solar cells, and the simulation of a 4H-SiC vertical junction FET in Sentaurus Device.
This issue highlights the new features and enhancements in Version Z-2007.03 of TCAD Sentaurus, TSUPREM-4™, Davinci, and Medici. There is also an article on extreme ultraviolet (EUV) lithography simulation.
The lead article examines full process flows that include lithography and topography simulations. There is an introduction to Fammos for interconnect stress and reliability analysis, as well as articles describing the design and optimization of double-halo 45-nm CMOS technology, the simulation of nanocrystal nonvolatile flash memory, and the enhancements to Raphael™ in Version Z-2006.12.
This edition has articles on adaptive meshing for power applications using Sentaurus Process, 3D IGBT power device simulation, TCAD simulation of silicon-carbide devices, and recent developments in gallium nitride (GaN) simulation using Sentaurus Device.
This issue highlights the new features and enhancements in Version Y-2006.06 of TCAD Sentaurus, TSUPREM-4™, Davinci, and Medici. There are also articles about process simulation using atomistic, state-of-the-art, kinetic Monte Carlo models, IGBT optimization using process compact models, and the topographic applications of Sentaurus Topography.
The latest developments in Sentaurus Device with regard to advanced optoelectronic simulations are featured in this edition. CMOS image sensors, solar cells, the calculation of microscopic gain, light-emitting diodes, and lasers are discussed.
The lead article looks at TCAD as a key component of Design for Manufacturing (DFM). This is followed by articles on the calibration work of the Consulting and Engineering Group, the impact of structure representation on the extraction of interconnect capacitance, the 3D modeling of stress history, and the 3D process and device simulations of a 25-nm NMOS Omega FinFET.
This issue highlights the first release of the new TCAD Sentaurus software (Version X-2005.10), created by combining the best-in-class features of Synopsys and former ISE TCAD products. In addition, updates to TSUPREM-4™, Davinci, and Medici in Version X-2005.10 are described.
This issue addresses advanced device simulation for stress engineering, stress-enhanced mobility in embedded SiGe PMOSFETs, stress engineering for aggressively scaled bulk MOSFETs, and modeling the effect of packaging stress on reliability and device performance.
The importance and pervasiveness of TCAD tools in power electronics, power circuits, and GaN power devices are discussed. Temperature issues with regard to power devices are presented as well.
This newsletter announces the acquisition of ISE Integrated Systems Engineering AG by Synopsys. It provides information about the Synopsys TCAD product roadmap and several articles that include 3D process and device simulation of stress effects, Monte Carlo simulation of implant into strained silicon, or SiGe, and III–V heterostructures, current collapse in FETs, nonlocal trap-assisted tunneling, and design optimization of nonvolatile memory.
This edition includes articles on the use of process compact models to analyze the impact of process parameters on device characteristics, an improved process flow for 3D NMOS transistors, the simulation of GaN devices using accurate band structure and gain models, and the introduction of both the kinetic Monte Carlo method and FRENDTECH models into FLOOPS-ISE.
In addition to the presentation of process and device simulations for strained silicon CMOS devices, other articles include geometry and mesh generation for nonvolatile memories, VCSEL optimization, improvements to ISE’s visualization tool that is based on Tecplot®, and CMOS image sensor simulations.