The cross-sectional view of the simulated hybrid orientation CMOS device on 100 Silicon handle wafer. The nMOSFETs and the pMOSFETs are created on local silicon patch with (100) and (110) surface orientation, respectively. These different local surfaces are created through successive etching, deposition and silicon selective epitaxy.
Important processing steps in creating the hybrid orientation substrate: 1) Deposition of a layer of silicon with (110) surface orientation on the substrate with (100) surface orientation, 2) shallow trench definition, 3) etching of the "110" silicon in the area reserved for the nMOSFET, and 4) selective epitaxial growth of silicon with (100) surface orientation on the "100" substrate only.
Compared to (100) substrates the hole mobility is much higher in MOSFETs fabricated on (110) or (111) substrates with conventional SiO2, as the highest piezoresistance coefficient is obtained on the (110) surface under compressive stress. For the electron mobility, longitudinal tensile stress is preferred on both (100) and (110) surface orientation. This opens up the possibility of designing a new technology flow with n-channel devices fabricated on (100) surface with channel orientation along <100> crystal plane, and the p-channel devices built on the (110) surface with the channel oriented in the <110/111> direction. This technology is called Hybrid orientation technology (HOT). Hybrid orientation technology has gained a lot of interest in the CMOS technology community due to the significant performance enhancement it provides.
Selective epitaxial growth is now becoming an essential technology for advanced CMOS with elevated S/D, SiGe pocket, etc. Moreover, silicon selective epitaxy is the key process step in HOT. The carrier mobility is dependent on the quality of the epitaxial layer and it has been found that the electron mobility on the (100) epi-Si can be even better than that of (100) control substrate and hole mobility on (110) epi-Si is 2.5 times more. Depending on the processing temperature condition, the epitaxial-growth may occur on insulators like nitride, etc. Hence a proper control on nucleation growth is very important for any kind of process simulation of selective epitaxial growth.
This application note showcases the HOT and selective EPI simulation support in Sentaurus Process for the example of a CMOS inverter. In a single 2d process simulation the nMOSFET and the pMOSFET, are created on local silicon patch with (100) and (110) surface orientation, respectively. Subsequently Sentaurus Device simulates the IV characteristics of the individual transistors as well as the static behavior (VTC) and dynamic behavior (transient pulse) of the entire CMOS inverter.
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