Seismos LX, a transistor-level design product, is the first in the EDA market to analyze stress and well proximity effects in circuit-level designs in nanometer technologies. Seismos LX computes the variation in mobility and threshold voltage of a transistor in a layout as a function of its proximity to STI, n/p well, or because of intentional stress introduced through ESL and DSL layers, and writes out an annotated SPICE netlist. With an easy to use graphical interface, one can visualize the stress maps for a transistor in a GDS layout and also vary the layout to simulate a “what if” scenario, and check on the effect of layout variation on changes in electrical characteristics of transistors in the viscinity.
- Enable circuit designers to simulate and optimize the layout dependency of silicon stress effects on device characteristics and circuit performance
- Handle a wide range of design sizes from a few transistors to multimillions of transistors with high performance and memory efficiency
- Annotate stress effects back to the SPICE netlist for circuit simulations
- Readily integrate into third-party design flows
- Provide a GUI mode for data visualization and real-time what-if analysis in a layout environment
- Quickly identify complex structures for further analysis in field solvers
- Ensure seamless integration with existing design flows