Videos

		2012 HSPICE SIG Event: Tackling Design Integrity of Multi-Gbps Systems On January 31, 2012, Synopsys hosted an HSPICE SIG Event in Santa Clara, CA. At this event, industry leaders spoke about their experiences using HSPICE in some of their most challenging designs. Tony Todesco, SMTS Design Engineer, AMD; Johann Nittman, Signal Integrity Engineer, Cavium Networks; Liping Li, Sr. Member of the Technical Staff, Altera; Randy Wolff, Manager, Signal Integrity R&D Group, Micron; Scott Wedge, Sr. Staff Engineer, Synopsys

		In-Design Physical Verification Milestone In this video, Synopsys Chairman and CEO, Dr. Aart de Geus shares his view on the broad and rapid adoption of this new technology and how it could change physical verification going forward. Dr. Aart de Geus, Synopsys Chairman and CEO

		Modern-era Custom Design Tired of using two-generations-old EDA technology for your next-generation mixed-signal IC? Synopsys’ new custom design solution can quickly bring you into the modern era of custom chip design. Joe Mastroianni, Synopsys VP of AMS R&D,

		Get the Best Performance from PrimeTime Karen Linser, staff applications engineer in Synopsys’ Implementation Group, describes a few easy ways for getting the best PrimeTime performance and achieving faster sign-off analysis. Karen Linser DOWNLOAD PRESENTATION (PDF)

		10X Faster Routing Runtime Combine advanced routing algorithms with multi-threading technology, and you get a speed increase of >10X on quad-core machines. Tong Gao, Synopsys Scientist and architect of Zroute

A System Level Design Strategy The Electronics Technology Channel Unifying or Overrated: A System Level Design Strategy Joachim Kunkel, Synopsys inc.

		Perspective: Boost your design productivity Design Compiler Graphical, the newest member of the Design Compiler product family, creates a better starting point for physical implementation and can shave weeks off your design schedule. Antun Domic, senior vice president and general manager of Synopsys' Implementation Group

		Small Delay Defects-The Need for Better At-Speed Tests Manufacturing process variations can introduce small delays that adversely affect critical design paths, leading to circuit failures. Dr. T.W. Williams introduces technology developed at Synopsys to detect defects creating these delays, thereby increasing the test quality. Tom Williams, Synopsys Fellow

		Perspective: How to Improve Design TTR John Chilton, senior vice president of Marketing and Business Development at Synopsys, talks about the importance of utilizing today’s widely-available multi-core processor-based compute infrastructures to accelerate design TTR. John Chilton, senior vice president of Marketing and Business Development at Synopsys