Videos 

George Mekhtarian, Product Marketing Manager in Synopsys’ Implementation Group highlights the latest features in PrimeTime.
George Mekhtarian, Product Marketing Manager

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ARM Cortex-A9 MPCore Multi-core Processor Hierarchical Implementation with IC Compiler Learn how ARM utilized IC Compiler’s concurrent hierarchical design for multi-core implementation, driving better performance as well as better throughput.
Philip Watson, Implementation Environment Program Manager

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IC Compiler: Routing and Design for Manufacturability (DFM) IC Compiler uses concurrent optimization techniques to simultaneously consider the impact of manufacturing rules, timing, and other design goals for high QoR and improved manufacturability.
Raj Varada, Principal Engineer

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Automatic Block Size Reduction with IC Compiler MinChip Technology IC Compiler reduces runtime and memory while delivering hand-craft-quality macro placement, MinChip die size reduction, clock tree synthesis, skew optimization, clock-gate merging, and more. STMicroelectronics achieved a huge reduction in die-size with a runtime of only 4 to 6 hours!
Naveen Raina, Technical Specialist

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Concurrent Hierarchical Design with IC Compiler, Real Life Application on Mobile Multi-Media Processor IC Compiler offers the industry’s first concurrent hierarchical design system that delivers a high degree of automation combined with high-quality optimization. Learn more about the results Toshiba achieved with the latest advances in IC Compiler.
Mutsunori Igarashi, Chief Specialist, Design Methodology Development

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John Chilton, senior vice president of Marketing and Business Development at Synopsys, talks about the importance of utilizing today’s widely-available multi-core processor-based compute infrastructures to accelerate design TTR.
John Chilton, senior vice president of Marketing and Business Development at Synopsys,